[U-Boot] [PATCH v2 01/10] ARM: dove: add support for Marvell Dove SoC
Prafulla Wadaskar
prafulla at marvell.com
Mon Feb 11 04:39:14 CET 2013
> -----Original Message-----
> From: Sebastian Hesselbarth [mailto:sebastian.hesselbarth at gmail.com]
> Sent: 04 December 2012 14:02
> To: Sebastian Hesselbarth
> Cc: u-boot at lists.denx.de; Rabeeh Khoury; Albert Aribaud; Prafulla
> Wadaskar; Andy Fleming; Joe Hershberger; Daniel Stodden; Luka Perkov
> Subject: [PATCH v2 01/10] ARM: dove: add support for Marvell Dove SoC
>
> This patch adds initial support for the armv7-based Marvell Dove SoC
> (88AP510).
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
I could not locate V3 of this patch in my inbox, so please consider these comments applicable for V3 if not changed between v2-to-v3.
> Changelog:
> v1->v2:
> - fix some commenting styles
>
> Cc: u-boot at lists.denx.de
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> Cc: Rabeeh Khoury <rabeeh at solid-run.com>
> Cc: Albert Aribaud <albert.u.boot at aribaud.net>
> Cc: Prafulla Wadaskar <prafulla at marvell.com>
> Cc: Andy Fleming <afleming at gmail.com>
> Cc: Joe Hershberger <joe.hershberger at gmail.com>
> Cc: Daniel Stodden <daniel.stodden at gmail.com>
> Cc: Luka Perkov <luka at openwrt.org>
> ---
> arch/arm/cpu/armv7/dove/Makefile | 49 +++++
> arch/arm/cpu/armv7/dove/cpu.c | 266
> ++++++++++++++++++++++++++
> arch/arm/cpu/armv7/dove/dram.c | 118 ++++++++++++
> arch/arm/cpu/armv7/dove/lowlevel_init.S | 83 ++++++++
> arch/arm/cpu/armv7/dove/mpp.c | 318
> +++++++++++++++++++++++++++++++
> arch/arm/cpu/armv7/dove/timer.c | 176 +++++++++++++++++
> arch/arm/cpu/armv7/dove/usb.c | 101 ++++++++++
> arch/arm/include/asm/arch-dove/config.h | 153 +++++++++++++++
> arch/arm/include/asm/arch-dove/cpu.h | 204 ++++++++++++++++++++
> arch/arm/include/asm/arch-dove/dove.h | 93 +++++++++
> arch/arm/include/asm/arch-dove/gpio.h | 35 ++++
> arch/arm/include/asm/arch-dove/mpp.h | 283
> +++++++++++++++++++++++++++
> 12 files changed, 1879 insertions(+)
> create mode 100644 arch/arm/cpu/armv7/dove/Makefile
> create mode 100644 arch/arm/cpu/armv7/dove/cpu.c
> create mode 100644 arch/arm/cpu/armv7/dove/dram.c
> create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S
> create mode 100644 arch/arm/cpu/armv7/dove/mpp.c
> create mode 100644 arch/arm/cpu/armv7/dove/timer.c
> create mode 100644 arch/arm/cpu/armv7/dove/usb.c
> create mode 100644 arch/arm/include/asm/arch-dove/config.h
> create mode 100644 arch/arm/include/asm/arch-dove/cpu.h
> create mode 100644 arch/arm/include/asm/arch-dove/dove.h
> create mode 100644 arch/arm/include/asm/arch-dove/gpio.h
> create mode 100644 arch/arm/include/asm/arch-dove/mpp.h
>
> diff --git a/arch/arm/cpu/armv7/dove/Makefile
> b/arch/arm/cpu/armv7/dove/Makefile
> new file mode 100644
> index 0000000..127d67e
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/Makefile
> @@ -0,0 +1,49 @@
> +#
> +# Marvell Dove SoC Makefile
> +#
> +# Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
I don't find a file CREDITs, either add it or remove above line :-)
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
Recommended: remove the above lines above and you may add the people to whom you wish to give credits here itself.
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(SOC).o
> +
> +SOBJS += lowlevel_init.o
> +COBJS-y := cpu.o dram.o timer.o mpp.o
> +COBJS-$(CONFIG_USB_EHCI_MARVELL) += usb.o
> +
> +COBJS := $(COBJS-y)
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
> +
> +all: $(obj).depend $(LIB)
> +
> +$(LIB): $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#####################################################################
> ####
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#####################################################################
> ####
> diff --git a/arch/arm/cpu/armv7/dove/cpu.c
> b/arch/arm/cpu/armv7/dove/cpu.c
> new file mode 100644
> index 0000000..b9e708c
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/cpu.c
> @@ -0,0 +1,266 @@
> +/*
> + * Marvell Dove SoC cpu related functions
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
Ditto
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <asm/cache.h>
> +#include <u-boot/md5.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +#include <hush.h>
> +
> +void reset_cpu(unsigned long ignored)
> +{
> + struct dovecpu_registers *cpureg =
> + (struct dovecpu_registers *)DOVE_CPU_REG_BASE;
> +
> + /* Enable soft reset to assert RSTOUTn */
> + writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
> + &cpureg->rstoutn_mask);
> + /* Assert soft reset */
> + writel(readl(&cpureg->sys_soft_rst) | 1,
May you please replace magic numbers with macros?
> + &cpureg->sys_soft_rst);
> + do {} while (1);
> +}
> +
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int dove_print_cpu(void)
> +{
> + char *cpu;
> + u32 idreg;
> + u16 part, rev;
> +
> + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(idreg));
> +
> + part = (idreg >> ARM_ID_PARTNUM_OFFSET) & ARM_ID_PARTNUM_MASK;
> + rev = (idreg >> ARM_ID_REVISION_OFFSET) & ARM_ID_REVISION_MASK;
> +
> + switch (part) {
> + case DOVECPU_PART_SHEEVA:
> + cpu = "Marvell Sheeva";
> + break;
> + default:
> + cpu = "Unknown CPU";
> + }
> +
> + printf("CPU: %s (rev %d)\n", cpu, rev);
There are more than one spaces in the display string, do you really need them? Please remove them.
> + return 0;
> +}
> +
> +int dove_print_soc(void)
> +{
> + char *soc, *rev;
> + u16 devid = (readl(DOVE_REG_PCIE_DEVID) >> 16) & 0xffff;
> + u8 revid = readl(DOVE_REG_PCIE_REVID) & 0xff;
> +
> + switch (devid) {
> + case DOVESOC_DEVID_AP510:
> + soc = "AP510";
> + break;
> + case DOVESOC_DEVID_F6781:
> + soc = "F6781";
> + break;
> + default:
> + printf("ERROR.. %s: Unsupported SoC %04x\n", __func__, devid);
> + return -1;
> + }
> +
> + switch (revid) {
> + case DOVESOC_REVID_Z0:
> + rev = "Z0";
> + break;
> + case DOVESOC_REVID_Z1:
> + rev = "Z1";
> + break;
> + case DOVESOC_REVID_Y0:
> + rev = "Y0";
> + break;
> + case DOVESOC_REVID_Y1:
> + rev = "Y1";
> + break;
> + case DOVESOC_REVID_X0:
> + rev = "X0";
> + break;
> + case DOVESOC_REVID_A0:
> + rev = "A0";
> + break;
> + case DOVESOC_REVID_A1:
> + rev = "A1";
> + break;
> + default:
> + rev = "Unknown revision";
> + };
> +
> + printf("SoC: Dove 88%s (%s)\n", soc, rev);
Same here...
> + return 0;
> +}
> +
> +int print_cpuinfo(void)
> +{
> + if (dove_print_soc())
> + return -1;
> + if (dove_print_cpu())
> + return -1;
> + return 0;
> +}
> +#endif /* CONFIG_DISPLAY_CPUINFO */
> +
> +/*
> + * dove_init_gpio - initial GPIO configuration
> + */
> +void dove_init_gpio(struct dove_gpio_init *gpp)
> +{
> + struct dovegpio_registers *gpio0reg =
> + (struct dovegpio_registers *)DOVE_GPIO0_BASE;
> + struct dovegpio_registers *gpio1reg =
> + (struct dovegpio_registers *)DOVE_GPIO1_BASE;
> + struct dovegpio_registers *gpio2reg =
> + (struct dovegpio_registers *)DOVE_GPIO2_BASE;
> +
> + /* Init GPIOS to default values as per board requirement */
> + writel(gpp->val0, &gpio0reg->dout);
> + writel(gpp->val1, &gpio1reg->dout);
> + writel(gpp->val2, &gpio2reg->dout);
> + writel(gpp->oe0_n, &gpio0reg->oe);
> + writel(gpp->oe1_n, &gpio1reg->oe);
> + writel(gpp->oe2_n, &gpio2reg->oe);
> +}
> +
> +/*
> + * Window Size
> + * Used with the Base register to set the address window size and
> location.
> + * Must be programmed from LSB to MSB as sequence of ones followed by
> + * sequence of zeros. The number of ones specifies the size of the
> window in
> + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16
> MByte).
> + * NOTE: A value of 0x0 specifies 64-KByte size.
> + */
> +unsigned int dove_winctrl_calcsize(unsigned int sizeval)
> +{
> + int i;
> + unsigned int j = 0;
> + u32 val = sizeval >> 1;
> +
> + for (i = 0; val >= 0x10000; i++) {
Please replace magic no by SZ_64K or something similar
> + j |= (1 << i);
> + val = val >> 1;
> + }
> + return 0x0000ffff & j;
Please replace with macro
> +}
> +
> +/*
> + * dove_config_adr_windows - Configure address Windows
> + *
> + * There are 8 address windows supported by Dove Soc to addess
> different
> + * devices. Windows 0-3 can be configured for size, BAR and remap
> addr.
> + * Windows 4-7 can be configured for size and BAR.
> + * Below configuration is standard for most of the cases
> + *
> + * If remap function not used, remap_lo must be set as base
> + */
> +int dove_config_adr_windows(void)
> +{
> + struct dovewin_registers *winregs =
> + (struct dovewin_registers *)DOVE_CPU_WIN_BASE;
> +
> + /* Window 0: 1M PCIE0 IO address space */
> + writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE0,
> + DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[0].ctrl);
> +
> + writel(DOVE_DEFADR_PCIE0_IO, &winregs[0].base);
> + writel(DOVE_DEFADR_PCIE0_IO_REMAP, &winregs[0].remap_lo);
> + writel(0x0, &winregs[0].remap_hi);
> +
> + /* Window 1: 1M PCIE1 IO address space */
> + writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PCIE1,
> + DOVECPU_ATTR_PCIE_IO, DOVECPU_WIN_ENABLE), &winregs[1].ctrl);
> +
> + writel(DOVE_DEFADR_PCIE1_IO, &winregs[1].base);
> + writel(DOVE_DEFADR_PCIE1_IO_REMAP, &winregs[1].remap_lo);
> + writel(0x0, &winregs[1].remap_hi);
> +
> + /* Window 2: 128M PCIE0 MEM address space */
> + writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE0,
> + DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE),
> &winregs[2].ctrl);
> +
> + writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].base);
> + writel(DOVE_DEFADR_PCIE0_MEM, &winregs[2].remap_lo);
> + writel(0x0, &winregs[2].remap_hi);
> +
> + /* Window 3: 128M PCIE1 MEM address space */
> + writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_PCIE1,
> + DOVECPU_ATTR_PCIE_MEM, DOVECPU_WIN_ENABLE),
> &winregs[3].ctrl);
> +
> + writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].base);
> + writel(DOVE_DEFADR_PCIE1_MEM, &winregs[3].remap_lo);
> + writel(0x0, &winregs[3].remap_hi);
> +
> + /* Window 4: 1M Cryptographic SRAM address space */
> + writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_SASRAM,
> + DOVECPU_ATTR_SASRAM, DOVECPU_WIN_ENABLE), &winregs[4].ctrl);
> + writel(DOVE_DEFADR_SASRAM, &winregs[4].base);
> +
> + /* Window 5: 128M Bootrom address space */
> + writel(DOVECPU_WIN_CTRL_DATA(SZ_128M, DOVECPU_TARGET_BOOTROM,
> + DOVECPU_ATTR_BOOTROM, DOVECPU_WIN_ENABLE), &winregs[5].ctrl);
> + writel(DOVE_DEFADR_BOOTROM, &winregs[5].base);
> +
> + /* Window 6: 1M PMU Scratchpad address space */
> + writel(DOVECPU_WIN_CTRL_DATA(SZ_1M, DOVECPU_TARGET_PMURAM,
> + DOVECPU_ATTR_PMURAM, DOVECPU_WIN_ENABLE), &winregs[6].ctrl);
> + writel(DOVE_DEFADR_PMURAM, &winregs[6].base);
> +
> + /* Window 7: Disabled */
> + writel(DOVECPU_WIN_DISABLE, &winregs[7].ctrl);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_ARCH_CPU_INIT
> +int arch_cpu_init(void)
> +{
> + dove_config_adr_windows();
> +#ifdef CONFIG_USB_EHCI_MARVELL
> + dove_ehci_phy_init(0);
> + dove_ehci_phy_init(1);
> +#endif /* CONFIG_USB_EHCI_MARVELL */
> + return 0;
> +}
> +#endif /* CONFIG_ARCH_CPU_INIT */
> +
> +void enable_caches(void)
> +{
> +#ifndef CONFIG_SYS_DCACHE_OFF
> + /* Enable D-cache. I-cache is already enabled in lowlevel_init.S
> */
> + dcache_enable();
> +#endif /* CONFIG_SYS_DCACHE_OFF */
> +}
> +
> +#ifdef CONFIG_MVGBE
> +int cpu_eth_init(bd_t *bis)
> +{
> + mvgbe_initialize(bis);
> + return 0;
> +}
> +#endif /* CONFIG_MVGBE */
> diff --git a/arch/arm/cpu/armv7/dove/dram.c
> b/arch/arm/cpu/armv7/dove/dram.c
> new file mode 100644
> index 0000000..437263c
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/dram.c
> @@ -0,0 +1,118 @@
> +/*
> + * Marvell Dove SoC DRAM initialization
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
Ditto
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define DOVE_REG_DRAM_MAP(x) (DOVE_REGISTER(0x800100) + (x * 0x10))
> +#define DRAM_START_MASK 0xff800000
> +#define DRAM_SIZE_MASK 0xf
> +#define DRAM_SIZE_SHIFT 16
> +
> +/*
> + * dove_sdram_start - reads start from Memory Address Map Register n
> + */
> +u32 dove_dram_start(enum memory_bank bank)
> +{
> + u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
> + u32 enable = 0x01 & reg;
> +
> + if ((!enable) || (bank > BANK1))
> + return 0;
> +
> + return reg & DRAM_START_MASK;
> +}
> +
> +/*
> + * dove_sdram_size - reads size from Memory Address Map Register n
> + */
> +u32 dove_dram_size(enum memory_bank bank)
> +{
> + u32 reg = readl(DOVE_REG_DRAM_MAP(bank));
> + u32 enable = 0x01 & reg;
> + u32 size;
> +
> + if ((!enable) || (bank > BANK1))
> + return 0;
> +
> + /*
> + * area_length: 7 = 8M, 8 = 16M, ..., 15 = 2048M
> + * size = 1 << (area_length + 16)
> + */
> + size = (reg >> DRAM_SIZE_SHIFT) & DRAM_SIZE_MASK;
> + size = 1 << (size + 16);
> + return size;
> +}
> +
> +#ifndef CONFIG_SYS_BOARD_DRAM_INIT
> +int dram_init(void)
> +{
> + int i;
> +
> + gd->ram_size = 0;
> + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> + gd->bd->bi_dram[i].start = dove_dram_start(i);
> + gd->bd->bi_dram[i].size = dove_dram_size(i);
> +
> + /*
> + * It is assumed that all memory banks are consecutive
> + * and without gaps.
> + * If the gap is found, ram_size will be reported for
> + * consecutive memory only
> + */
> + if (gd->bd->bi_dram[i].start != gd->ram_size)
> + break;
> +
> + gd->ram_size += gd->bd->bi_dram[i].size;
> +
> + }
> +
> + for (; i < CONFIG_NR_DRAM_BANKS; i++) {
> + /*
> + * If above loop terminated prematurely, we need to set
> + * remaining banks' start address & size as 0. Otherwise other
> + * u-boot functions and Linux kernel gets wrong values which
> + * could result in crash
> + */
> + gd->bd->bi_dram[i].start = 0;
> + gd->bd->bi_dram[i].size = 0;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * If this function is not defined here,
> + * board.c alters dram bank zero configuration defined above.
> + */
> +void dram_init_banksize(void)
> +{
> + dram_init();
Please correct indentation here, use tab
> +}
> +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
> diff --git a/arch/arm/cpu/armv7/dove/lowlevel_init.S
> b/arch/arm/cpu/armv7/dove/lowlevel_init.S
> new file mode 100644
> index 0000000..105d12d
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/lowlevel_init.S
> @@ -0,0 +1,83 @@
> +/*
> + * Marvell Dove SoC icache and reg base low level init
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/arch/dove.h>
> +#include <generated/asm-offsets.h>
> +#include <linux/linkage.h>
> +
> +/*
> + * Enable Tauros2 L2 ICache
> + */
> +.macro init_l2cc
> + mrc 15, 0, r0, c1, c0, 1
> + orr r0, r0, #0x2
> + mcr 15, 0, r0, c1, c0, 1
> +.endm /* init_l2cc */
> +
> +/*
> + * Init internal register base addresses
> + */
> +.macro init_reg_base
> + /* set SB reg base to 0xf1000000 */
> + ldr r1, =(DOVE_PREMAP_INT_REGS_BASE_ADDR)
> + ldr r6, =DOVE_SB_REGS_PHYS_BASE
> + str r6, [r1]
> +
> + /* set NB reg base to 0xf1800000 */
> + ldr r1, =(DOVE_CPU_CTRL_REG)
> + ldr r4, =0xffff0000
> + ldr r6, [r1]
> + and r6, r6, r4
> + ldr r4, =DOVE_NB_REGS_PHYS_BASE
> + lsr r4, r6, #16
> + orr r6, r6, r4
> + str r6, [r1]
> +
> + /* Set AXI bridge address mapping to 0xf1800000 */
> + ldr r1, =(DOVE_AXI_CTRL_REG)
> + ldr r4, =0x007fffff
> + ldr r6, [r1]
> + and r6, r6, r4
> + ldr r4, =DOVE_NB_REGS_PHYS_BASE
> + orr r6, r6, r4
> + str r6, [r1]
> +
> + /* set MC configuration register decode address to 0xf1800000 */
> + ldr r1, =(DOVE_PREMAP_MC_DECODE_REG)
> + ldr r4, =0x0000ffff
> + ldr r6, [r1]
> + and r6, r6, r4
> + ldr r4, =DOVE_NB_REGS_PHYS_BASE
> + orr r6, r6, r4
> + str r6, [r1]
> +
> +.endm /* init_reg_base */
> +
> +.section ".text.init", "x"
> +
> +ENTRY(lowlevel_init)
> + init_l2cc
> + init_reg_base
> +
> + /* r12 saved upper lr*/
> + mov pc,lr
> +ENDPROC(lowlevel_init)
> diff --git a/arch/arm/cpu/armv7/dove/mpp.c
> b/arch/arm/cpu/armv7/dove/mpp.c
> new file mode 100644
> index 0000000..ed24b38
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/mpp.c
> @@ -0,0 +1,318 @@
> +/*
> + * Marvell Dove SoC MPP pinmux
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +#include <asm/arch/mpp.h>
> +#include <asm/arch/gpio.h>
> +
> +#define MPP_BITS 4
> +#define MPP_MASK 0xf
> +#define MPPS_PER_REG 8
> +
> +#define MPP_NUM(_x) ((_x) & 0xff)
> +#define MPP_SEL(_x) (((_x) >> 8) & 0x1f)
> +#define MPP_GPIO(_x) ((_x) & (1 << 15))
> +
> +#define MPP_CTRL(i) (DOVE_MPP_BASE + (i * MPP_BITS))
> +#define MPP_PMU_GENERAL_CTRL (DOVE_MPP_BASE + 0x010)
> +#define PMUG_AUDIO0_AC97_SEL (1 << 16)
> +#define MPP4_CTRL (DOVE_MPP_BASE + 0x240)
> +#define MPP4_SDIO0_GPIO_SEL (1 << 0)
> +#define MPP4_SDIO1_GPIO_SEL (1 << 1)
> +#define MPP4_CAMERA_GPIO_SEL (1 << 2)
> +#define MPP4_AUDIO1_GPIO_SEL (1 << 3)
> +#define MPP4_UART1_GPIO_SEL (1 << 4)
> +#define MPP4_SPI_GPIO_SEL (1 << 5)
> +#define MPP_GENERAL_CTRL (DOVE_PDMA_BASE + 0x403c)
> +#define MPPG_NAND_GPIO_SEL (1 << 0)
> +#define MPPG_AUDIO1_SPDIFO_GPIO_SEL (1 << 1)
> +#define GENERAL_CONFIG_1 (DOVE_PDMA_BASE + 0x002c)
> +#define GENERAL_TWSI_MUXEN_OPTION1 (1 << 7)
> +#define GENERAL_CONFIG_2 (DOVE_PDMA_BASE + 0x0030)
> +#define GENERAL_TWSI_OPTION3_SEL (1 << 22)
> +#define GENERAL_TWSI_MUXEN_OPTION3 (1 << 21)
> +#define GENERAL_TWSI_MUXEN_OPTION2 (1 << 20)
> +#define SSP_CONFIG_STATUS_1 (DOVE_PDMA_BASE + 0x0034)
> +#define SSP_SSP_ON_AUDIO1 (1 << 0)
> +
> +/*
> + * MPP0-23 have standard MPP register layout
> + */
> +static void dove_mpp_std_set(u16 config)
> +{
> + u8 num = MPP_NUM(config);
> + u32 off = (num / MPPS_PER_REG) * MPP_BITS;
> + u32 shift = (num % MPPS_PER_REG) * MPP_BITS;
> + u32 reg;
> +
> + /* configure standard MPP pin */
> + reg = readl(MPP_CTRL(off));
> + reg &= ~(MPP_MASK << shift);
> + reg |= MPP_SEL(config) << shift;
> + writel(reg, MPP_CTRL(off));
> +
> + /* configure gpio capabilities */
> + if (MPP_GPIO(config))
> + orion_gpio_set_valid(num, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> + else
> + orion_gpio_set_valid(num, 0);
Why it is orion_gpio*? it should be generic API call or SoC specific.
> +}
> +
> +/*
> + * MPP0-15 also allow to mux PMU functions
> + */
> +static void dove_mpp_pmu_set(u16 config)
> +{
> + u8 num = MPP_NUM(config);
> +
> + if (MPP_SEL(config) == PMU) {
> + /* enable PMU on MPP */
> + writel(readl(MPP_PMU_GENERAL_CTRL) | (1 << num),
> + MPP_PMU_GENERAL_CTRL);
> + /* disable gpio capabilities */
> + orion_gpio_set_valid(num, 0);
I think you are trying to reuse the framework implemented by orion,
You may move generic part from orion to common area so that you can use it. Using other SoC direct calls doesn't sound good to me.
> + } else {
> + /* disable PMU on MPP */
> + writel(readl(MPP_PMU_GENERAL_CTRL) & ~(1 << num),
> + MPP_PMU_GENERAL_CTRL);
> + /* configure MPP */
> + dove_mpp_std_set(config);
> + }
> +}
> +
> +/*
> + * MPP groups on MPP4_CTRL have different register layout
> + * and allow GPIO or special function only
> + */
> +static void dove_mpp4_set(u16 config)
> +{
> + u32 reg = readl(MPP4_CTRL);
> + u32 mask;
> + u8 n, nmin, nmax;
> + int gpio;
> +
> + switch (MPP_NUM(config)) {
> + case MPP_CAMERA:
> + mask = MPP4_CAMERA_GPIO_SEL;
> + nmin = MPP_CAMERA;
> + nmax = MPP_CAMERA_MAX;
> + break;
> + case MPP_SDIO0:
> + mask = MPP4_SDIO0_GPIO_SEL;
> + nmin = MPP_SDIO0;
> + nmax = MPP_SDIO0_MAX;
> + break;
> + case MPP_SDIO1:
> + mask = MPP4_SDIO1_GPIO_SEL;
> + nmin = MPP_SDIO1;
> + nmax = MPP_SDIO1_MAX;
> + break;
> + case MPP_SPI:
> + mask = MPP4_SPI_GPIO_SEL;
> + nmin = MPP_SPI;
> + nmax = MPP_SPI_MAX;
> + break;
> + case MPP_UART1:
> + mask = MPP4_UART1_GPIO_SEL;
> + nmin = MPP_UART1;
> + nmax = MPP_UART1_MAX;
> + break;
> + default:
> + return;
> + }
> +
> + reg &= ~mask;
> + if (MPP_SEL(config))
> + reg |= mask;
> + writel(reg, MPP4_CTRL);
> +
> + /* configure gpio capabilities */
> + gpio = 0;
> + if (MPP_GPIO(config))
> + gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
> + for (n = nmin; n <= nmax; n++)
> + orion_gpio_set_valid(n, gpio);
> +}
> +
> +/*
> + * MPP_GENERAL_CTRL allows GPIO on NAND pins
> + */
> +static void dove_mpp_nand_set(u16 config)
> +{
> + u32 reg = readl(MPP_GENERAL_CTRL);
> + u8 n;
> + int gpio;
> +
> + reg &= ~MPPG_NAND_GPIO_SEL;
> + if (config == MPP_NAND_GPO)
> + reg |= MPPG_NAND_GPIO_SEL;
> + writel(reg, MPP_GENERAL_CTRL);
> +
> + /* configure gpio capabilities */
> + gpio = (config == MPP_NAND_GPO) ? GPIO_OUTPUT_OK : 0;
> + for (n = MPP_NAND; n <= MPP_NAND_MAX; n++)
> + orion_gpio_set_valid(n, gpio);
> +}
> +
> +/*
> + * Dedicated audio1 pins can carry i2s, spdif, ssp or twsi
> + * and gpio in various combinations
> + */
> +#define AUDIO1_TWSI (1 << 0)
> +#define AUDIO1_SPDIFO (1 << 1)
> +#define AUDIO1_SSP (1 << 2)
> +#define AUDIO1_GPIO (1 << 3)
Move these defined on the top of in header file; preferred in header.
> +
> +static void dove_mpp_audio1_set(u16 config)
> +{
> + u32 mpp4 = readl(MPP4_CTRL);
> + u32 sspc1 = readl(SSP_CONFIG_STATUS_1);
> + u32 gmpp = readl(MPP_GENERAL_CTRL);
> + u32 gcfg2 = readl(GENERAL_CONFIG_2);
> + u8 n, sel = MPP_SEL(config);
> + int gpio;
> +
> + gcfg2 &= ~GENERAL_TWSI_OPTION3_SEL;
> + gmpp &= ~MPPG_AUDIO1_SPDIFO_GPIO_SEL;
> + sspc1 &= ~SSP_SSP_ON_AUDIO1;
> + mpp4 &= ~MPP4_AUDIO1_GPIO_SEL;
> + if (sel & AUDIO1_TWSI)
> + gcfg2 |= GENERAL_TWSI_OPTION3_SEL;
> + if (sel & AUDIO1_SPDIFO)
> + gmpp |= MPPG_AUDIO1_SPDIFO_GPIO_SEL;
> + if (sel & AUDIO1_SSP)
> + sspc1 |= SSP_SSP_ON_AUDIO1;
> + if (sel & AUDIO1_GPIO)
> + mpp4 |= MPP4_AUDIO1_GPIO_SEL;
> +
> + writel(mpp4, MPP4_CTRL);
> + writel(sspc1, SSP_CONFIG_STATUS_1);
> + writel(gmpp, MPP_GENERAL_CTRL);
> + writel(gcfg2, GENERAL_CONFIG_2);
> +
> + /* gpio allows gpio on all audio1 mpp pins */
> + gpio = 0;
> + if (config == MPP_AUDIO1_GPIO)
> + gpio = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
> +
> + for (n = MPP_AUDIO1; n <= MPP_AUDIO1_MAX; n++)
> + orion_gpio_set_valid(n, gpio);
> +
> + switch (config) {
> + /* spdifo and twsi allow gpio on mpp[52:55] */
> + case MPP_AUDIO1_SPDIFO:
> + case MPP_AUDIO1_TWSI:
> + orion_gpio_set_valid(52, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> + orion_gpio_set_valid(53, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> + orion_gpio_set_valid(54, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> + orion_gpio_set_valid(55, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> + break;
> + /* i2s and ssp allow gpio on mpp[56:57] */
> + case MPP_AUDIO1_I2S:
> + case MPP_AUDIO1_SSP:
> + orion_gpio_set_valid(56, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> + orion_gpio_set_valid(57, GPIO_INPUT_OK | GPIO_OUTPUT_OK);
> + break;
> + }
> +}
> +
> +/*
> + * MPP PMU switches audio0 pins to ac97 or i2s0
> + */
> +static void dove_mpp_audio0_set(u16 config)
> +{
> + /* switch i2s or ac97 to audio0 */
> + u32 reg = readl(MPP_PMU_GENERAL_CTRL);
> +
> + reg &= ~PMUG_AUDIO0_AC97_SEL;
> + if (config == MPP_AUDIO0_AC97)
> + reg |= PMUG_AUDIO0_AC97_SEL;
> + writel(reg, MPP_PMU_GENERAL_CTRL);
> +}
> +
> +/*
> + * TWSI has 3 optional pin sets that can be switched during runtime
> + */
> +static void dove_mpp_twsi_set(u16 config)
> +{
> + u32 gcfg1 = readl(GENERAL_CONFIG_1);
> + u32 gcfg2 = readl(GENERAL_CONFIG_2);
> +
> + gcfg1 &= ~GENERAL_TWSI_MUXEN_OPTION1;
> + gcfg2 &= ~(GENERAL_TWSI_MUXEN_OPTION2 |
> GENERAL_TWSI_MUXEN_OPTION3);
> +
> + switch (config) {
> + case MPP_TWSI_OPTION1:
> + gcfg1 |= GENERAL_TWSI_MUXEN_OPTION1;
> + break;
> + case MPP_TWSI_OPTION2:
> + gcfg2 |= GENERAL_TWSI_MUXEN_OPTION2;
> + break;
> + case MPP_TWSI_OPTION3:
> + gcfg2 |= GENERAL_TWSI_MUXEN_OPTION3;
> + break;
> + }
> +
> + writel(gcfg1, GENERAL_CONFIG_1);
> + writel(gcfg2, GENERAL_CONFIG_2);
> +}
> +
> +void dove_mpp_conf(u16 *mpp_list)
> +{
> + while (*mpp_list) {
> + u8 num = MPP_NUM(*mpp_list);
> +
> + if (num <= MPP_PMU_MAX)
> + dove_mpp_pmu_set(*mpp_list);
> + else if (num <= MPP_STD_MAX)
> + dove_mpp_std_set(*mpp_list);
> + else {
> + switch (num) {
> + case MPP_CAMERA:
> + case MPP_SDIO0:
> + case MPP_SDIO1:
> + case MPP_SPI:
> + case MPP_UART1:
> + dove_mpp4_set(*mpp_list);
> + break;
> + case MPP_NAND:
> + dove_mpp_nand_set(*mpp_list);
> + break;
> + case MPP_AUDIO0:
> + dove_mpp_audio0_set(*mpp_list);
> + break;
> + case MPP_AUDIO1:
> + dove_mpp_audio1_set(*mpp_list);
> + break;
> + case MPP_TWSI:
> + dove_mpp_twsi_set(*mpp_list);
> + break;
> + }
> + }
> + mpp_list++;
> + }
> +}
> diff --git a/arch/arm/cpu/armv7/dove/timer.c
> b/arch/arm/cpu/armv7/dove/timer.c
> new file mode 100644
> index 0000000..3be9b78
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/timer.c
> @@ -0,0 +1,176 @@
> +/*
> + * Marvell Dove SoC timer
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +
There are two blank lines here,
Pls remove one.
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/dove.h>
> +
> +#define UBOOT_CNTR 0 /* counter to use for uboot timer */
> +
> +/* Timer reload and current value registers */
> +struct dovetmr_val {
> + u32 reload; /* Timer reload reg */
> + u32 val; /* Timer value reg */
> +};
> +
> +/* Timer registers */
> +struct dovetmr_registers {
> + u32 ctrl; /* Timer control reg */
> + u32 pad[3];
> + struct dovetmr_val tmr[2];
> + u32 wdt_reload;
> + u32 wdt_val;
> +};
> +
> +struct dovetmr_registers *dovetmr_regs =
> + (struct dovetmr_registers *)DOVE_TIMER_BASE;
> +
> +/*
> + * ARM Timers Registers Map
> + */
> +#define CNTMR_CTRL_REG &dovetmr_regs->ctrl
> +#define CNTMR_RELOAD_REG(tmrnum) &dovetmr_regs->tmr[tmrnum].reload
> +#define CNTMR_VAL_REG(tmrnum) &dovetmr_regs->tmr[tmrnum].val
> +
> +/*
> + * ARM Timers Control Register
> + * CPU_TIMERS_CTRL_REG (CTCR)
> + */
> +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
> +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
> +#define CTCR_ARM_TIMER_EN(cntr) (1 <<
> CTCR_ARM_TIMER_EN_OFFS(cntr))
> +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
> +
> +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
> +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
> +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 <<
> CTCR_ARM_TIMER_AUTO_OFFS(cntr))
> +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 <<
> CTCR_ARM_TIMER_AUTO_OFFS(cntr))
> +
> +/*
> + * ARM Timer\Watchdog Reload Register
> + * CNTMR_RELOAD_REG (TRR)
> + */
> +#define TRG_ARM_TIMER_REL_OFFS 0
> +#define TRG_ARM_TIMER_REL_MASK 0xffffffff
> +
> +/*
> + * ARM Timer\Watchdog Register
> + * CNTMR_VAL_REG (TVRG)
> + */
> +#define TVR_ARM_TIMER_OFFS 0
> +#define TVR_ARM_TIMER_MASK 0xffffffff
> +#define TVR_ARM_TIMER_MAX 0xffffffff
> +#define TIMER_LOAD_VAL 0xffffffff
> +
> +#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
> + (CONFIG_SYS_TCLK / 1000))
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define timestamp gd->tbl
> +#define lastdec gd->lastinc
> +
> +ulong get_timer_masked(void)
> +{
> + ulong now = READ_TIMER;
> +
> + if (lastdec >= now) {
> + /* normal mode */
> + timestamp += lastdec - now;
> + } else {
> + /* we have an overflow ... */
> + timestamp += lastdec +
> + (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
> + }
> + lastdec = now;
> +
> + return timestamp;
> +}
> +
> +ulong get_timer(ulong base)
> +{
> + return get_timer_masked() - base;
> +}
> +
> +void __udelay(unsigned long usec)
> +{
> + uint current;
> + ulong delayticks;
> +
> + current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
> + delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
> +
> + if (current < delayticks) {
> + delayticks -= current;
> + do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current);
> + do {} while ((TIMER_LOAD_VAL - delayticks) <
> + readl(CNTMR_VAL_REG(UBOOT_CNTR)));
> + } else {
> + do {} while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
> + (current - delayticks));
> + }
> +}
> +
> +/*
> + * init the counter
> + */
> +int timer_init(void)
> +{
> + unsigned int cntmrctrl;
> +
> + /* load value into timer */
> + writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
> + writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
> +
> + /* enable timer in auto reload mode */
> + cntmrctrl = readl(CNTMR_CTRL_REG);
> + cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
> + cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
> + writel(cntmrctrl, CNTMR_CTRL_REG);
> +
> + /* init the timestamp and lastdec value */
> + lastdec = READ_TIMER;
> + timestamp = 0;
> +
> + return 0;
> +}
> +
> +/*
> + * This function is derived from PowerPC code (read timebase as long
Does these comments stands valid, I think you reference is Kirkwood.
> long).
> + * On ARM it just returns the timer value.
> + */
> +unsigned long long get_ticks(void)
> +{
> + return get_timer(0);
> +}
> +
> +/*
> + * This function is derived from PowerPC code (timebase clock
> frequency).
> + * On ARM it returns the number of timer ticks per second.
> + */
> +ulong get_tbclk(void)
> +{
> + return (ulong)CONFIG_SYS_HZ;
> +}
> diff --git a/arch/arm/cpu/armv7/dove/usb.c
> b/arch/arm/cpu/armv7/dove/usb.c
> new file mode 100644
> index 0000000..1b932db
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/dove/usb.c
> @@ -0,0 +1,101 @@
> +/*
> + * Marvell Dove SoC USB PHY init
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/dove.h>
> +
> +/* Dove USB2.0 PHY registers */
> +#define USB20_POWER_CTRL ((base) + 0x400)
> +#define USB20_PHY_PLL_CTRL ((base) + 0x410)
> +#define PHY_PLL_VCO_RECALIBRATE (1 << 21)
> +#define USB20_PHY_TX_CTRL ((base) + 0x420)
> +#define PHY_TX_HS_STRESS_CTRL (1 << 31)
> +#define PHY_TX_BLOCK_EN (1 << 21)
> +#define PHY_TX_IMP_CAL_VTH(x) (x << 14)
> +#define PHY_TX_IMP_CAL_VTH_MASK PHY_TX_IMP_CAL_VTH(0x7)
> +#define PHY_TX_RCAL_START (1 << 12)
> +#define PHY_TX_LOWVDD_EN (1 << 11)
> +#define USB20_PHY_RX_CTRL ((base) + 0x430)
> +#define PHY_RX_EDGE_DET(x) (x << 26)
> +#define PHY_RX_EDGE_DET_MASK PHY_RX_EDGE_DET(0x3)
> +#define PHY_RX_CDR_FASTLOCK_EN (1 << 21)
> +#define PHY_RX_SQ_LENGTH(x) (x << 15)
> +#define PHY_RX_SQ_LENGTH_MASK PHY_RX_SQ_LENGTH(0x3)
> +#define PHY_RX_SQ_THRESH(x) (x << 4)
> +#define PHY_RX_SQ_THRESH_MASK PHY_RX_SQ_THRESH(0xf)
> +#define PHY_RX_LPF_COEFF(x) (x << 2)
> +#define PHY_RX_LPF_COEFF_MASK PHY_RX_LPF_COEFF(0x3)
> +#define USB20_PHY_IVREF_CTRL ((base) + 0x440)
> +#define PHY_IVREF_TXVDD12(x) (x << 8)
> +#define PHY_IVREF_TXVDD12_MASK PHY_IVREF_TXVDD12(0x3)
> +#define USB20_PHY_TESTGRP_CTRL ((base) + 0x450)
> +#define PHY_TESTGRP_SQ_RST (1 << 15)
> +
> +void dove_ehci_phy_init(int port)
> +{
> + u32 base = (port == 0) ? DOVE_USB20_0_BASE : DOVE_USB20_1_BASE;
> + u32 reg;
> +
> + /* USB PHY PLL control */
> + reg = readl(USB20_PHY_PLL_CTRL);
> + writel(reg | PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
> + udelay(100);
> + writel(reg & ~PHY_PLL_VCO_RECALIBRATE, USB20_PHY_PLL_CTRL);
> +
> + /* USB PHY Tx control */
> + reg = readl(USB20_PHY_TX_CTRL);
> + reg &= ~PHY_TX_IMP_CAL_VTH_MASK;
> + reg |= PHY_TX_IMP_CAL_VTH(0x5);
> + reg |= PHY_TX_LOWVDD_EN;
> + reg |= PHY_TX_RCAL_START;
> + reg |= PHY_TX_BLOCK_EN;
> + reg |= PHY_TX_HS_STRESS_CTRL;
> + writel(reg, USB20_PHY_TX_CTRL);
> + udelay(100);
> + writel(reg & ~PHY_TX_RCAL_START, USB20_PHY_TX_CTRL);
> +
> + /* USB PHY RX control */
> + reg = readl(USB20_PHY_RX_CTRL);
> + reg &= ~(PHY_RX_LPF_COEFF_MASK | PHY_RX_SQ_THRESH_MASK |
> + PHY_RX_SQ_LENGTH_MASK | PHY_RX_EDGE_DET_MASK);
> + reg |= PHY_RX_LPF_COEFF(0x1);
> + reg |= PHY_RX_SQ_THRESH(0xc);
> + reg |= PHY_RX_SQ_LENGTH(0x1);
> + reg |= PHY_RX_EDGE_DET(0x0);
> + reg &= ~PHY_RX_CDR_FASTLOCK_EN;
> + writel(reg, USB20_PHY_RX_CTRL);
> +
> + /* USB PHY IVREF control */
> + reg = readl(USB20_PHY_IVREF_CTRL);
> + reg &= ~PHY_IVREF_TXVDD12_MASK;
> + reg |= PHY_IVREF_TXVDD12(0x3);
> + writel(reg, USB20_PHY_IVREF_CTRL);
> +
> + /* USB PHY TEST GROUP control */
> + reg = readl(USB20_PHY_TESTGRP_CTRL);
> + reg &= ~PHY_TESTGRP_SQ_RST;
> + writel(reg, USB20_PHY_TESTGRP_CTRL);
> +}
> diff --git a/arch/arm/include/asm/arch-dove/config.h
> b/arch/arm/include/asm/arch-dove/config.h
> new file mode 100644
> index 0000000..2d94a48
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/config.h
> @@ -0,0 +1,153 @@
> +/*
> + * Marvell SoC config
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_CONFIG_H
> +#define _DOVE_CONFIG_H
> +
> +#include <asm/arch/dove.h>
> +
> +#define CONFIG_ARMV7 /* Basic Architecture */
> +#define CONFIG_DOVE /* SOC Family Name */
> +#define CONFIG_SHEEVA_88SV581 /* CPU Core subversion */
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> + /* default Dcache Line length for Dove */
> +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
> +#define CONFIG_SYS_DCACHE_OFF /* Disable DCache by default */
> +
> +/*
> + * By default kwbimage.cfg from board specific folder is used
I think you should use dvbimage.cfg naming convention, since kwb stands for Kirkwood boot image, same way it will be dove boot image
> + * If for some board, different configuration file need to be used,
> + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header
> file
> + */
> +#ifndef CONFIG_SYS_KWD_CONFIG
> +#define CONFIG_SYS_KWD_CONFIG
> $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
> +#endif /* CONFIG_SYS_KWD_CONFIG */
Same: change all references to DOVE, secondly do you think DV is better than DOVE to shorten then name everywhere like KW for Kirkwood?
> +
> +/* Dove has 2k of Security SRAM, use it for SP */
> +#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
> +#define CONFIG_NR_DRAM_BANKS_MAX 2
> +
> +#define CONFIG_I2C_MVTWSI_BASE DOVE_TWSI_BASE
> +#define MV_UART_CONSOLE_BASE DOVE_UART0_BASE
> +#define MV_SATA_BASE DOVE_SATA_BASE
> +#define MV_SATA_PORT0_OFFSET DOVE_SATA_PORT0_OFFSET
> +
> +/*
> + * NAND configuration
> + */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_NAND_KIRKWOOD 1
> +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
> +#define NAND_ALLOW_ERASE_ALL 1
> +#endif
> +
> +/*
> + * SPI Flash configuration
> + */
> +#ifdef CONFIG_CMD_SF
> +#define CONFIG_HARD_SPI 1
> +#define CONFIG_ORION_SPI 1
> +#define ORION_SPI_BASE DOVE_SPI_BASE
???
> +#ifndef CONFIG_ENV_SPI_BUS
> +# define CONFIG_ENV_SPI_BUS 0
> +#endif
> +#ifndef CONFIG_ENV_SPI_CS
> +# define CONFIG_ENV_SPI_CS 0
> +#endif
> +#ifndef CONFIG_ENV_SPI_MAX_HZ
> +# define CONFIG_ENV_SPI_MAX_HZ 25000000
> +#endif
> +#endif
> +
> +/*
> + * Ethernet Driver configuration
> + */
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_CMD_MII
> +#define CONFIG_NETCONSOLE /* include NetConsole support */
> +#define CONFIG_PHYLIB
> +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
> +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
> +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
> +#endif /* CONFIG_CMD_NET */
> +
> +/*
> + * SDHCI
> + */
> +#ifdef CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_MMC
> +#define CONFIG_MMC_SDMA
> +#define CONFIG_SDHCI
> +#define CONFIG_DOVE_SDHCI /* Enable Dove SDHCI controller driver
> */
> +#define CONFIG_MMC_SDHCI_IO_ACCESSORS
> +#define CONFIG_SYS_MMC_MAX_DEVICE 2
> +#endif
> +
> +/*
> + * USB/EHCI
> + */
> +#ifdef CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI_MARVELL
> +#define CONFIG_EHCI_IS_TDI
> +#endif /* CONFIG_CMD_USB */
> +
> +/*
> + * IDE Support on SATA ports
> + */
> +#ifdef CONFIG_CMD_IDE
> +#define __io
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_MVSATA_IDE
> +#define CONFIG_IDE_PREINIT
> +#define CONFIG_MVSATA_IDE_USE_PORT1
> +/* Needs byte-swapping for ATA data register */
> +#define CONFIG_IDE_SWAP_IO
> +/* Data, registers and alternate blocks are at the same offset */
> +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
> +#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
> +#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
> +/* Each 8-bit ATA register is aligned to a 4-bytes address */
> +#define CONFIG_SYS_ATA_STRIDE 4
> +/* Controller supports 48-bits LBA addressing */
> +#define CONFIG_LBA48
> +/* CONFIG_CMD_IDE requires some #defines for ATA registers */
> +#define CONFIG_SYS_IDE_MAXBUS 2
> +#define CONFIG_SYS_IDE_MAXDEVICE 2
> +/* ATA registers base is at SATA controller base */
> +#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
> +#endif /* CONFIG_CMD_IDE */
> +
> +/*
> + * I2C related stuff
> + */
> +#ifdef CONFIG_CMD_I2C
> +#ifndef CONFIG_SOFT_I2C
> +#define CONFIG_I2C_MVTWSI
> +#endif
> +#define CONFIG_SYS_I2C_SLAVE 0x0
> +#define CONFIG_SYS_I2C_SPEED 100000
> +#endif
> +
> +#endif /* _DOVE_CONFIG_H */
> diff --git a/arch/arm/include/asm/arch-dove/cpu.h
> b/arch/arm/include/asm/arch-dove/cpu.h
> new file mode 100644
> index 0000000..718dd59
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/cpu.h
> @@ -0,0 +1,204 @@
> +/*
> + * Marvell Dove SoC CPU
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVECPU_H
> +#define _DOVECPU_H
> +
> +#include <asm/system.h>
> +
> +#ifndef __ASSEMBLY__
> +
Please give the reference of the SoC documentation that you are referring here for all enums and macros.
> +#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target
> << 4) \
> + | (attr << 8) | (dove_winctrl_calcsize(size) << 16))
> +
> +#define DOVEGBE_PORT_SERIAL_CONTROL1_REG (DOVE_EGIGA_BASE + 0x44c)
> +#define DOVE_REG_PCIE_DEVID (DOVE_REG_PCIE0_BASE + 0x00)
> +#define DOVE_REG_PCIE_REVID (DOVE_REG_PCIE0_BASE + 0x08)
> +#define DOVE_REG_SYSRST_CNT (DOVE_MPP_BASE + 0x50)
> +#define SYSRST_CNT_1SEC_VAL (25*1000000)
> +#define DOVE_REG_MPP_OUT_DRV_REG (DOVE_MPP_BASE + 0xE0)
> +
> +enum memory_bank {
> + BANK0,
> + BANK1,
> +};
> +
> +enum dovecpu_winen {
> + DOVECPU_WIN_DISABLE,
> + DOVECPU_WIN_ENABLE
> +};
> +
> +enum dovecpu_target {
> + DOVECPU_TARGET_DRAM = 0x0,
> + DOVECPU_TARGET_SASRAM = 0x3,
> + DOVECPU_TARGET_NAND = 0xc,
> + DOVECPU_TARGET_PMURAM = 0xd,
> + DOVECPU_TARGET_PCIE0 = 0x4,
> + DOVECPU_TARGET_PCIE1 = 0x8,
> + DOVECPU_TARGET_SPI = 0x1,
> + DOVECPU_TARGET_BOOTROM = 0x1,
> +};
> +
> +enum dovecpu_attrib {
> + DOVECPU_ATTR_DRAM = 0x00,
> + DOVECPU_ATTR_SASRAM = 0x00,
> + DOVECPU_ATTR_NAND = 0x00,
> + DOVECPU_ATTR_PMURAM = 0x00,
> + DOVECPU_ATTR_PCIE_IO = 0xe0,
> + DOVECPU_ATTR_PCIE_MEM = 0xe8,
> + DOVECPU_ATTR_SPI0 = 0xfe,
> + DOVECPU_ATTR_SPI1 = 0xfb,
> + DOVECPU_ATTR_BOOTROM = 0xfd,
> +};
> +
> +enum dovecpu_part {
> + DOVECPU_PART_SHEEVA = 0x581,
> +};
> +
> +enum dovesoc_devid {
> + DOVESOC_DEVID_F6781 = 0x6781,
> + DOVESOC_DEVID_AP510 = 0x0510,
> +};
> +
> +enum dovesoc_revid {
> + DOVESOC_REVID_Z0 = 0,
> + DOVESOC_REVID_Z1 = 1,
> + DOVESOC_REVID_Y0 = 2,
> + DOVESOC_REVID_Y1 = 3,
> + DOVESOC_REVID_X0 = 4,
> + DOVESOC_REVID_A0 = 6,
> + DOVESOC_REVID_A1 = 7,
> +};
> +
> +/*
> + * Default Device Address MAP BAR values
> + */
> +#define DOVE_DEFADR_PCIE0_MEM 0xe0000000
> +#define DOVE_DEFADR_PCIE0_IO 0xf2000000
> +#define DOVE_DEFADR_PCIE0_IO_REMAP 0x00000000
> +#define DOVE_DEFADR_PCIE1_MEM 0xe8000000
> +#define DOVE_DEFADR_PCIE1_IO 0xf2100000
> +#define DOVE_DEFADR_PCIE1_IO_REMAP 0x00100000
> +#define DOVE_DEFADR_SASRAM 0xc8000000
> +#define DOVE_DEFADR_BOOTROM 0xf8000000
> +#define DOVE_DEFADR_PMURAM 0xf0000000
> +
> +/*
> + * ARM CPUID register
> + */
> +#define ARM_ID_REVISION_OFFSET 0
> +#define ARM_ID_REVISION_MASK 0xf
> +#define ARM_ID_PARTNUM_OFFSET 4
> +#define ARM_ID_PARTNUM_MASK 0xfff
> +#define ARM_ID_ARCH_OFFSET 16
> +#define ARM_ID_ARCH_MASK 0xf
> +#define ARM_ID_VAR_OFFSET 20
> +#define ARM_ID_VAR_MASK 0xf
> +#define ARM_ID_ASCII_OFFSET 24
> +#define ARM_ID_ASCII_MASK 0xff
> +
> +/*
> + * read feroceon/sheeva core extra feature register
> + * using co-proc instruction
> + */
> +static inline unsigned int readfr_extra_feature_reg(void)
> +{
> + unsigned int val;
> + asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
> + (val) : : "cc");
> + return val;
> +}
> +
> +/*
> + * write feroceon/sheeva core extra feature register
> + * using co-proc instruction
> + */
> +static inline void writefr_extra_feature_reg(unsigned int val)
> +{
> + asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
> + (val) : "cc");
> + isb();
> +}
> +
> +/*
> + * Downstream Bridge Registers
> + */
> +struct dovewin_registers {
> + u32 ctrl;
> + u32 base;
> + u32 remap_lo;
> + u32 remap_hi;
> +};
> +
> +/*
> + * CPU control and status Registers
> + */
> +struct dovecpu_registers {
> + u32 config; /* 0x20100 */
> + u32 ctrl_stat; /* 0x20104 */
> + u32 rstoutn_mask; /* 0x20108 */
> + u32 sys_soft_rst; /* 0x2010C */
> + u32 bridge_cause_irq; /* 0x20110 */
> + u32 bridge_mask_irq; /* 0x20114 */
> + u32 pad1;
> + u32 pmu_ctrl; /* 0x2011c */
> +};
Same here, documentation reference is needed.
> +
> +/*
> + * GPIO 0/1 Registers
> + * GPIO 2 Registers (no datain/irq)
> + */
> +struct dovegpio_registers {
> + u32 dout;
> + u32 oe;
> + u32 blink_en;
> + u32 din_pol;
> + u32 din;
> + u32 irq_cause;
> + u32 irq_mask;
> + u32 irq_level;
> +};
> +
> +struct dove_gpio_init {
> + u32 val0;
> + u32 val1;
> + u32 val2;
> + u32 oe0_n;
> + u32 oe1_n;
> + u32 oe2_n;
> +};
Pls move to gpio.h
> +
> +/*
> + * functions
> + */
> +void reset_cpu(unsigned long ignored);
> +unsigned char get_random_hex(void);
> +u32 dove_dram_start(enum memory_bank bank);
> +u32 dove_dram_size(enum memory_bank bank);
> +int dove_config_adr_windows(void);
> +void dove_init_gpio(struct dove_gpio_init *);
> +unsigned int dove_winctrl_calcsize(unsigned int sizeval);
> +
> +#endif /* __ASSEMBLY__ */
> +#endif /* _DOVECPU_H */
> diff --git a/arch/arm/include/asm/arch-dove/dove.h
> b/arch/arm/include/asm/arch-dove/dove.h
> new file mode 100644
> index 0000000..da5011b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/dove.h
> @@ -0,0 +1,93 @@
> +/*
> + * Marvell Dove SoC register offsets and config
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_H
> +#define _DOVE_H
> +
> +/* Dove TCLK is fixed to 166MHz */
> +#define CONFIG_SYS_TCLK 166666667
> +
> +/* SOC specific definitions */
> +#define DOVE_PREMAP_REGS_PHYS_BASE 0xd0000000
> +#define DOVE_PREMAP_INT_REGS_BASE_ADDR (DOVE_PREMAP_REGS_PHYS_BASE +
> 0x20080)
> +#define DOVE_PREMAP_MC_DECODE_REG (DOVE_PREMAP_REGS_PHYS_BASE +
> 0x800010)
> +
> +#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
> +#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
> +#define DOVE_REGISTER(x) (DOVE_SB_REGS_PHYS_BASE + x)
> +
> +#define DOVE_AXI_CTRL_REG (DOVE_REGISTER(0xd0224))
> +#define DOVE_CPU_CTRL_REG (DOVE_REGISTER(0xd025c))
> +#define DOVE_MC_CTRL_REG (DOVE_REGISTER(0xd0260))
> +#define DOVE_MC_DECODE_REG (DOVE_REGISTER(0x800010))
> +
> +#define DOVE_SPI_BASE (DOVE_REGISTER(0x10600))
> +#define DOVE_TWSI_BASE (DOVE_REGISTER(0x11000))
> +#define DOVE_UART0_BASE (DOVE_REGISTER(0x12000))
> +#define DOVE_UART1_BASE (DOVE_REGISTER(0x12100))
> +#define DOVE_UART2_BASE (DOVE_REGISTER(0x12200))
> +#define DOVE_UART3_BASE (DOVE_REGISTER(0x12300))
> +#define DOVE_CPU_WIN_BASE (DOVE_REGISTER(0x20000))
> +#define DOVE_CPU_REG_BASE (DOVE_REGISTER(0x20100))
> +#define DOVE_TIMER_BASE (DOVE_REGISTER(0x20300))
> +#define DOVE_REG_PCIE0_BASE (DOVE_REGISTER(0x40000))
> +#define DOVE_REG_PCIE1_BASE (DOVE_REGISTER(0x80000))
> +#define DOVE_USB20_0_BASE (DOVE_REGISTER(0x50000))
> +#define DOVE_USB20_1_BASE (DOVE_REGISTER(0x51000))
> +#define DOVE_EGIGA_BASE (DOVE_REGISTER(0x72000))
> +#define DOVE_SDIO1_BASE (DOVE_REGISTER(0x90000))
> +#define DOVE_SDIO0_BASE (DOVE_REGISTER(0x92000))
> +#define DOVE_CAMERA_BASE (DOVE_REGISTER(0x94000))
> +#define DOVE_SATA_BASE (DOVE_REGISTER(0xa0000))
> +#define DOVE_NANDF_BASE (DOVE_REGISTER(0xc0000))
> +#define DOVE_PMU_BASE (DOVE_REGISTER(0xd0000))
> +#define DOVE_MPP_BASE (DOVE_REGISTER(0xd0200))
> +#define DOVE_GPIO0_BASE (DOVE_REGISTER(0xd0400))
> +#define DOVE_GPIO1_BASE (DOVE_REGISTER(0xd0420))
> +#define DOVE_RTC_BASE (DOVE_REGISTER(0xd8500))
> +#define DOVE_AC97_BASE (DOVE_REGISTER(0xe0000))
> +#define DOVE_PDMA_BASE (DOVE_REGISTER(0xe4000))
> +#define DOVE_GPIO2_BASE (DOVE_REGISTER(0xe8400))
> +#define DOVE_SSP_BASE (DOVE_REGISTER(0xec000))
> +
> +/* Dove Sata controller has one port */
> +#define DOVE_SATA_PORT0_OFFSET 0x2000
> +
> +/* Dove GbE controller has one port */
> +#define MAX_MVGBE_DEVS 1
> +#define MVGBE0_BASE DOVE_EGIGA_BASE
> +
> +/* Dove USB Host controller */
> +#define MVUSB0_BASE DOVE_USB20_0_BASE
> +#define MVUSB0_CPU_ATTR_DRAM_CS0 DOVECPU_ATTR_DRAM
> +#define MVUSB0_CPU_ATTR_DRAM_CS1 DOVECPU_ATTR_DRAM
> +#define MVUSB0_CPU_ATTR_DRAM_CS2 DOVECPU_WIN_DISABLE
> +#define MVUSB0_CPU_ATTR_DRAM_CS3 DOVECPU_WIN_DISABLE
> +
> +/* Dove CPU memory windows */
> +#define MVCPU_WIN_CTRL_DATA DOVECPU_WIN_CTRL_DATA
> +#define MVCPU_WIN_ENABLE DOVECPU_WIN_ENABLE
> +#define MVCPU_WIN_DISABLE DOVECPU_WIN_DISABLE
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-dove/gpio.h
> b/arch/arm/include/asm/arch-dove/gpio.h
> new file mode 100644
> index 0000000..71bef8e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/gpio.h
> @@ -0,0 +1,35 @@
> +/*
> + * Marvell Dove SoC gpio
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef __DOVE_GPIO_H
> +#define __DOVE_GPIO_H
> +
> +#include <orion_gpio.h>
> +
> +#define GPIO_MAX 70
> +#define GPIO_BASE(pin) (((pin) >= 64) ? DOVE_GPIO2_BASE : \
> + ((pin) >= 32) ? DOVE_GPIO1_BASE : \
> + DOVE_GPIO0_BASE)
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-dove/mpp.h
> b/arch/arm/include/asm/arch-dove/mpp.h
> new file mode 100644
> index 0000000..1279ac2
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/mpp.h
> @@ -0,0 +1,283 @@
> +/*
> + * Marvell Dove SoC pinmux
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_MPP_H
> +#define _DOVE_MPP_H
> +
> +#define DOVE_GPI (1 << 0)
> +#define DOVE_GPO (1 << 1)
> +#define DOVE_GPIO (DOVE_GPO | DOVE_GPI)
> +
> +#define MPP(_num, _sel, _gpio) ( \
> + /* MPP number */ ((_num) & 0xff) | \
> + /* MPP select value */ (((_sel) & 0x1f) << 8) | \
> + /* is gpio config */ ((!!(_gpio)) << 15))
> +
> +/* MPP0-15 allow PMU function */
> +#define MPP_PMU_MAX 15
> +#define PMU (0x10)
> +/* MPP0-23 have standard mpp register layout */
> +#define MPP_STD_MAX 23
> +
> +#define MPP0 0
> +#define MPP0_GPIO MPP(0, 0x0, 1)
> +#define MPP0_UART2_RTS MPP(0, 0x2, 0)
> +#define MPP0_SDIO0_CD MPP(0, 0x3, 0)
> +#define MPP0_LCD0_PWM MPP(0, 0xf, 0)
> +#define MPP0_PMU MPP(0, PMU, 0)
> +
> +#define MPP1 1
> +#define MPP1_GPIO MPP(1, 0x0, 1)
> +#define MPP1_UART2_CTS MPP(1, 0x2, 0)
> +#define MPP1_SDIO0_WP MPP(1, 0x3, 0)
> +#define MPP1_LCD1_PWM MPP(1, 0xf, 0)
> +#define MPP1_PMU MPP(1, PMU, 0)
> +
> +#define MPP2 2
> +#define MPP2_GPIO MPP(2, 0x0, 1)
> +#define MPP2_SATA_PRSNT MPP(2, 0x1, 0)
> +#define MPP2_UART2_TXD MPP(2, 0x2, 0)
> +#define MPP2_SDIO0_BUSPWR MPP(2, 0x3, 0)
> +#define MPP2_UART1_RTS MPP(2, 0x4, 0)
> +#define MPP2_PMU MPP(2, PMU, 0)
> +
> +#define MPP3 3
> +#define MPP3_GPIO MPP(3, 0x0, 1)
> +#define MPP3_SATA_ACT MPP(3, 0x1, 0)
> +#define MPP3_UART2_RXD MPP(3, 0x2, 0)
> +#define MPP3_SDIO0_LEDCTRL MPP(3, 0x3, 0)
> +#define MPP3_UART1_CTS MPP(3, 0x4, 0)
> +#define MPP3_LCD_SPI_CS1 MPP(3, 0xf, 0)
> +#define MPP3_PMU MPP(3, PMU, 0)
> +
> +#define MPP4 4
> +#define MPP4_GPIO MPP(4, 0x0, 1)
> +#define MPP4_UART3_RTS MPP(4, 0x2, 0)
> +#define MPP4_SDIO1_CD MPP(4, 0x3, 0)
> +#define MPP4_SPI1_MISO MPP(4, 0x4, 0)
> +#define MPP4_PMU MPP(4, PMU, 0)
> +
> +#define MPP5 5
> +#define MPP5_GPIO MPP(5, 0x0, 1)
> +#define MPP5_UART3_CTS MPP(5, 0x2, 0)
> +#define MPP5_SDIO1_WP MPP(5, 0x3, 0)
> +#define MPP5_SPI1_CS MPP(5, 0x4, 0)
> +#define MPP5_PMU MPP(5, PMU, 0)
> +
> +#define MPP6 6
> +#define MPP6_GPIO MPP(6, 0x0, 1)
> +#define MPP6_UART3_TXD MPP(6, 0x2, 0)
> +#define MPP6_SDIO1_BUSPWR MPP(6, 0x3, 0)
> +#define MPP6_SPI1_MOSI MPP(6, 0x4, 0)
> +#define MPP6_PMU MPP(6, PMU, 0)
> +
> +#define MPP7 7
> +#define MPP7_GPIO MPP(7, 0x0, 1)
> +#define MPP7_UART3_RXD MPP(7, 0x2, 0)
> +#define MPP7_SDIO1_LEDCTRL MPP(7, 0x3, 0)
> +#define MPP7_SPI1_SCK MPP(7, 0x4, 0)
> +#define MPP7_PMU MPP(7, PMU, 0)
> +
> +#define MPP8 8
> +#define MPP8_GPIO MPP(8, 0x0, 1)
> +#define MPP8_WATCHDOG_RSTOUT MPP(8, 0x1, 0)
> +#define MPP8_PMU MPP(8, PMU, 0)
> +
> +#define MPP9 9
> +#define MPP9_GPIO MPP(9, 0x0, 1)
> +#define MPP9_PEX1_CLKREQ MPP(9, 0x5, 0)
> +#define MPP9_PMU MPP(9, PMU, 0)
> +
> +#define MPP10 10
> +#define MPP10_GPIO MPP(10, 0x0, 1)
> +#define MPP10_SSP_SCLK MPP(10, 0x5, 0)
> +#define MPP10_PMU MPP(10, PMU, 0)
> +
> +#define MPP11 11
> +#define MPP11_GPIO MPP(11, 0x0, 1)
> +#define MPP11_SATA_PRSNT MPP(11, 0x1, 0)
> +#define MPP11_SATA_ACT MPP(11, 0x2, 0)
> +#define MPP11_SDIO0_LEDCTRL MPP(11, 0x3, 0)
> +#define MPP11_SDIO1_LEDCTRL MPP(11, 0x4, 0)
> +#define MPP11_PEX0_CLKREQ MPP(11, 0x5, 0)
> +#define MPP11_PMU MPP(11, PMU, 0)
> +
> +#define MPP12 12
> +#define MPP12_GPIO MPP(12, 0x0, 1)
> +#define MPP12_SATA_ACT MPP(12, 0x1, 0)
> +#define MPP12_UART2_RTS MPP(12, 0x2, 0)
> +#define MPP12_AUDIO0_EXTCLK MPP(12, 0x3, 0)
> +#define MPP12_SDIO1_CD MPP(12, 0x4, 0)
> +#define MPP12_PMU MPP(12, PMU, 0)
> +
> +#define MPP13 13
> +#define MPP13_GPIO MPP(13, 0x0, 1)
> +#define MPP13_UART2_CTS MPP(13, 0x2, 0)
> +#define MPP13_AUDIO1_EXTCLK MPP(13, 0x3, 0)
> +#define MPP13_SDIO1_WP MPP(13, 0x4, 0)
> +#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0)
> +#define MPP13_PMU MPP(13, PMU, 0)
> +
> +#define MPP14 14
> +#define MPP14_GPIO MPP(14, 0x0, 1)
> +#define MPP14_UART2_TXD MPP(14, 0x2, 0)
> +#define MPP14_SDIO1_BUSPWR MPP(14, 0x4, 0)
> +#define MPP14_SSP_TXD MPP(14, 0x5, 0)
> +#define MPP14_PMU MPP(14, PMU, 0)
> +
> +#define MPP15 15
> +#define MPP15_GPIO MPP(15, 0x0, 1)
> +#define MPP15_UART2_RXD MPP(15, 0x2, 0)
> +#define MPP15_SDIO1_LEDCTRL MPP(15, 0x4, 0)
> +#define MPP15_SSP_SFRM MPP(15, 0x5, 0)
> +#define MPP15_PMU MPP(15, PMU, 0)
> +
> +#define MPP16 16
> +#define MPP16_GPIO MPP(16, 0x0, 1)
> +#define MPP16_UART3_RTS MPP(16, 0x2, 0)
> +#define MPP16_SDIO0_CD MPP(16, 0x3, 0)
> +#define MPP16_LCD_SPI_CS1 MPP(16, 0x4, 0)
> +#define MPP16_AC97_SDI1 MPP(16, 0x5, 0)
> +
> +#define MPP17 17
> +#define MPP17_GPIO MPP(17, 0x0, 1)
> +#define MPP17_AC97_SYSCLKO MPP(17, 0x1, 0)
> +#define MPP17_UART3_CTS MPP(17, 0x2, 0)
> +#define MPP17_SDIO0_WP MPP(17, 0x3, 0)
> +#define MPP17_TWSI_SDA MPP(17, 0x4, 0)
> +#define MPP17_AC97_SDI2 MPP(17, 0x5, 0)
> +
> +#define MPP18 18
> +#define MPP18_GPIO MPP(18, 0x0, 1)
> +#define MPP18_UART3_TXD MPP(18, 0x2, 0)
> +#define MPP18_SDIO0_BUSPWR MPP(18, 0x3, 0)
> +#define MPP18_LCD0_PWM MPP(18, 0x4, 0)
> +#define MPP18_AC97_SDI3 MPP(18, 0x5, 0)
> +
> +#define MPP19 19
> +#define MPP19_GPIO MPP(19, 0x0, 1)
> +#define MPP19_UART3_RXD MPP(19, 0x2, 0)
> +#define MPP19_SDIO0_LEDCTRL MPP(19, 0x3, 0)
> +#define MPP19_TWSI_SCK MPP(19, 0x4, 0)
> +
> +#define MPP20 20
> +#define MPP20_GPIO MPP(20, 0x0, 1)
> +#define MPP20_AC97_SYSCLKO MPP(20, 0x1, 0)
> +#define MPP20_LCD_SPI_MISO MPP(20, 0x2, 0)
> +#define MPP20_SDIO1_CD MPP(20, 0x3, 0)
> +#define MPP20_SDIO0_CD MPP(20, 0x5, 0)
> +#define MPP20_SPI1_MISO MPP(20, 0x6, 0)
> +
> +#define MPP21 21
> +#define MPP21_GPIO MPP(21, 0x0, 1)
> +#define MPP21_UART1_RTS MPP(21, 0x1, 0)
> +#define MPP21_LCD_SPI_CS0 MPP(21, 0x2, 0)
> +#define MPP21_SDIO1_WP MPP(21, 0x3, 0)
> +#define MPP21_SSP_SFRM MPP(21, 0x4, 0)
> +#define MPP21_SDIO0_WP MPP(21, 0x5, 0)
> +#define MPP21_SPI1_CS MPP(21, 0x6, 0)
> +
> +#define MPP22 22
> +#define MPP22_GPIO MPP(22, 0x0, 1)
> +#define MPP22_UART1_CTS MPP(22, 0x1, 0)
> +#define MPP22_LCD_SPI_MOSI MPP(22, 0x2, 0)
> +#define MPP22_SDIO1_BUSPWR MPP(22, 0x3, 0)
> +#define MPP22_SSP_TXD MPP(22, 0x4, 0)
> +#define MPP22_SDIO0_BUSPWR MPP(22, 0x5, 0)
> +#define MPP22_SPI1_MOSI MPP(22, 0x6, 0)
> +
> +#define MPP23 23
> +#define MPP23_GPIO MPP(23, 0x0, 1)
> +#define MPP23_LCD_SPI_SCK MPP(23, 0x2, 0)
> +#define MPP23_SDIO1_LEDCTRL MPP(23, 0x3, 0)
> +#define MPP23_SSP_SCLK MPP(23, 0x4, 0)
> +#define MPP23_SDIO0_LEDCTRL MPP(23, 0x5, 0)
> +#define MPP23_SPI1_SCK MPP(23, 0x6, 0)
> +
> +/* MPP_CAMERA = MPP[24:39] */
> +#define MPP_CAMERA 24
> +#define MPP_CAMERA_CAMERA MPP(24, 0x0, 0)
> +#define MPP_CAMERA_GPIO MPP(24, 0x1, 1)
> +#define MPP_CAMERA_MAX 39
> +
> +/* MPP_SDIO0 = MPP[40:45] */
> +#define MPP_SDIO0 40
> +#define MPP_SDIO0_SDIO MPP(40, 0x0, 0)
> +#define MPP_SDIO0_GPIO MPP(40, 0x1, 1)
> +#define MPP_SDIO0_MAX 45
> +
> +/* MPP_SDIO1 = MPP[46:51] */
> +#define MPP_SDIO1 46
> +#define MPP_SDIO1_SDIO MPP(46, 0x0, 0)
> +#define MPP_SDIO1_GPIO MPP(46, 0x1, 1)
> +#define MPP_SDIO1_MAX 51
> +
> +/* MPP_AUDIO1 = MPP[52:57] */
> +#define MPP_AUDIO1 52
> +#define MPP_AUDIO1_I2S_SPDIFO MPP(52, 0x0, 0)
> +#define MPP_AUDIO1_I2S MPP(52, 0x2, 0)
> +#define MPP_AUDIO1_SPDIFO MPP(52, 0x8, 0)
> +#define MPP_AUDIO1_GPIO MPP(52, 0xa, 1)
> +#define MPP_AUDIO1_TWSI MPP(52, 0xb, 0)
> +#define MPP_AUDIO1_SSP_SPDIFO MPP(52, 0xc, 0)
> +#define MPP_AUDIO1_SSP MPP(52, 0xe, 0)
> +#define MPP_AUDIO1_SSP_TWSI MPP(52, 0xf, 0)
> +#define MPP_AUDIO1_MAX 57
> +
> +/* MPP_SPI = MPP[58:61] */
> +#define MPP_SPI 58
> +#define MPP_SPI_SPI MPP(58, 0x0, 0)
> +#define MPP_SPI_GPIO MPP(58, 0x1, 1)
> +#define MPP_SPI_MAX 61
> +
> +/* MPP_UART1 = MPP[62:63] */
> +#define MPP_UART1 62
> +#define MPP_UART1_UART1 MPP(62, 0x0, 0)
> +#define MPP_UART1_GPIO MPP(62, 0x1, 1)
> +#define MPP_UART1_MAX 63
> +
> +/* MPP_NAND = MPP[64:71] */
> +#define MPP_NAND 64
> +#define MPP_NAND_NAND MPP(64, 0x0, 0)
> +#define MPP_NAND_GPO MPP(64, 0x1, 1)
> +#define MPP_NAND_MAX 71
> +
> +/* MPP_AUDIO0 = Internal AC97/I2S mux for audio0 pins */
> +#define MPP_AUDIO0 72
> +#define MPP_AUDIO0_I2S MPP(72, 0x0, 0)
> +#define MPP_AUDIO0_AC97 MPP(72, 0x1, 0)
> +
> +/* MPP_TWSI = Internal TWSI option mux */
> +#define MPP_TWSI 73
> +#define MPP_TWSI_NONE MPP(73, 0x0, 0)
> +#define MPP_TWSI_OPTION1 MPP(73, 0x1, 0)
> +#define MPP_TWSI_OPTION2 MPP(73, 0x2, 0)
> +#define MPP_TWSI_OPTION3 MPP(73, 0x3, 0)
> +
> +#define MPP_MAX MPP_TWSI
> +
> +u8 dove_mpp_get_gpio_caps(u8 num);
> +void dove_mpp_conf(u16 *mpp_list);
> +
> +#endif
> --
> 1.7.10.4
Regards...
Prafulla . . .
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