[U-Boot] [PATCH 6/6] i.MX6: Add DDR controller registers
Liu Hui-R64343
r64343 at freescale.com
Mon Feb 18 06:16:43 CET 2013
>-----Original Message-----
>From: Eric Nelson [mailto:eric.nelson at boundarydevices.com]
>Sent: Monday, February 18, 2013 3:24 AM
>To: u-boot at lists.denx.de
>Cc: sbabic at denx.de; Liu Hui-R64343; Estevam Fabio-R49496;
>troy.kisky at boundarydevices.com; Eric Nelson
>Subject: [PATCH 6/6] i.MX6: Add DDR controller registers
>
>Signed-off-by: Eric Nelson <eric.nelson at boundarydevices.com>
>---
> arch/arm/include/asm/arch-mx6/mx6-ddr.h | 85
>+++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/mx6dl-ddr.h | 71
>++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/mx6q-ddr.h | 69
>+++++++++++++++++++++++
> 3 files changed, 225 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-mx6/mx6-ddr.h
> create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
> create mode 100644 arch/arm/include/asm/arch-mx6/mx6q-ddr.h
I did not see any user of these files, what the purpose of this?
>
>diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
>b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
>new file mode 100644
>index 0000000..4d18ede
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
>@@ -0,0 +1,85 @@
>+/*
>+ * Copyright (C) 2012 Boundary Devices Inc.
Either 2013 or 2012 - 2013?
>+ *
>+ * This program is free software; you can redistribute it and/or modify
>+ * it under the terms of the GNU General Public License as published by
>+ * the Free Software Foundation; either version 2 of the License, or
>+ * (at your option) any later version.
>+
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+
>+ * You should have received a copy of the GNU General Public License
>+along
>+ * with this program; if not, write to the Free Software Foundation,
>+Inc.,
>+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>+ */
>+#ifndef __ASM_ARCH_MX6_DDR_H__
>+#define __ASM_ARCH_MX6_DDR_H__
>+
>+#ifdef CONFIG_MX6Q
>+#include "mx6q-ddr.h"
>+#else
>+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #include
>+"mx6dl-ddr.h"
>+#else
>+#error "Please select cpu"
>+#endif /* CONFIG_MX6DL or CONFIG_MX6S */
>+#endif /* CONFIG_MX6Q */
>+
>+#define MMDC_P0_MDCTL 0x021b0000
I also prefer to add MX6_ prefix,
>+#define MMDC_P0_MDPDC 0x021b0004
>+#define MMDC_P0_MDOTC 0x021b0008
>+#define MMDC_P0_MDCFG0 0x021b000c
>+#define MMDC_P0_MDCFG1 0x021b0010
>+#define MMDC_P0_MDCFG2 0x021b0014
>+#define MMDC_P0_MDMISC 0x021b0018
>+#define MMDC_P0_MDSCR 0x021b001c
>+#define MMDC_P0_MDREF 0x021b0020
>+#define MMDC_P0_MDRWD 0x021b002c
>+#define MMDC_P0_MDOR 0x021b0030
>+#define MMDC_P0_MDASP 0x021b0040
>+#define MMDC_P0_MAPSR 0x021b0404
>+#define MMDC_P0_MPZQHWCTRL 0x021b0800
>+#define MMDC_P0_MPWLDECTRL0 0x021b080c
>+#define MMDC_P0_MPWLDECTRL1 0x021b0810
>+#define MMDC_P0_MPODTCTRL 0x021b0818
>+#define MMDC_P0_MPRDDQBY0DL 0x021b081c
>+#define MMDC_P0_MPRDDQBY1DL 0x021b0820
>+#define MMDC_P0_MPRDDQBY2DL 0x021b0824
>+#define MMDC_P0_MPRDDQBY3DL 0x021b0828
>+#define MMDC_P0_MPDGCTRL0 0x021b083c
>+#define MMDC_P0_MPDGCTRL1 0x021b0840
>+#define MMDC_P0_MPRDDLCTL 0x021b0848
>+#define MMDC_P0_MPWRDLCTL 0x021b0850
>+#define MMDC_P0_MPMUR0 0x021b08b8
>+
>+#define MMDC_P1_MDCTL 0x021b4000
>+#define MMDC_P1_MDPDC 0x021b4004
>+#define MMDC_P1_MDOTC 0x021b4008
>+#define MMDC_P1_MDCFG0 0x021b400c
>+#define MMDC_P1_MDCFG1 0x021b4010
>+#define MMDC_P1_MDCFG2 0x021b4014
>+#define MMDC_P1_MDMISC 0x021b4018
>+#define MMDC_P1_MDSCR 0x021b401c
>+#define MMDC_P1_MDREF 0x021b4020
>+#define MMDC_P1_MDRWD 0x021b402c
>+#define MMDC_P1_MDOR 0x021b4030
>+#define MMDC_P1_MDASP 0x021b4040
>+#define MMDC_P1_MAPSR 0x021b4404
>+#define MMDC_P1_MPZQHWCTRL 0x021b4800
>+#define MMDC_P1_MPWLDECTRL0 0x021b480c
>+#define MMDC_P1_MPWLDECTRL1 0x021b4810
>+#define MMDC_P1_MPODTCTRL 0x021b4818
>+#define MMDC_P1_MPRDDQBY0DL 0x021b481c
>+#define MMDC_P1_MPRDDQBY1DL 0x021b4820
>+#define MMDC_P1_MPRDDQBY2DL 0x021b4824
>+#define MMDC_P1_MPRDDQBY3DL 0x021b4828
>+#define MMDC_P1_MPDGCTRL0 0x021b483c
>+#define MMDC_P1_MPDGCTRL1 0x021b4840
>+#define MMDC_P1_MPRDDLCTL 0x021b4848
>+#define MMDC_P1_MPWRDLCTL 0x021b4850
>+#define MMDC_P1_MPMUR0 0x021b48b8
Ditto,
>+
>+#endif /*__ASM_ARCH_MX6_DDR_H__ */
>diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
>b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
>new file mode 100644
>index 0000000..02c272d
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
>@@ -0,0 +1,71 @@
>+/*
>+ * Copyright (C) 2012 Boundary Devices Inc.
Either 2013 or 2012 - 2013?
>+ *
>+ * This program is free software; you can redistribute it and/or modify
>+ * it under the terms of the GNU General Public License as published by
>+ * the Free Software Foundation; either version 2 of the License, or
>+ * (at your option) any later version.
>+
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+
>+ * You should have received a copy of the GNU General Public License
>+along
>+ * with this program; if not, write to the Free Software Foundation,
>+Inc.,
>+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>+ */
>+#ifndef __ASM_ARCH_MX6DLS_DDR_H__
>+#define __ASM_ARCH_MX6DLS_DDR_H__
>+
>+#ifndef CONFIG_MX6DL
>+#ifndef CONFIG_MX6S
>+#error "wrong CPU"
>+#endif
>+#endif
>+
>+#define IOM_DRAM_DQM0 0x020e0470
>+#define IOM_DRAM_DQM1 0x020e0474
>+#define IOM_DRAM_DQM2 0x020e0478
>+#define IOM_DRAM_DQM3 0x020e047c
>+#define IOM_DRAM_DQM4 0x020e0480
>+#define IOM_DRAM_DQM5 0x020e0484
>+#define IOM_DRAM_DQM6 0x020e0488
>+#define IOM_DRAM_DQM7 0x020e048c
>+
>+#define IOM_DRAM_CAS 0x020e0464
>+#define IOM_DRAM_RAS 0x020e0490
>+#define IOM_DRAM_RESET 0x020e0494
>+#define IOM_DRAM_SDCLK_0 0x020e04ac
>+#define IOM_DRAM_SDCLK_1 0x020e04b0
>+#define IOM_DRAM_SDBA2 0x020e04a0
>+#define IOM_DRAM_SDCKE0 0x020e04a4
>+#define IOM_DRAM_SDCKE1 0x020e04a8
>+#define IOM_DRAM_SDODT0 0x020e04b4
>+#define IOM_DRAM_SDODT1 0x020e04b8
>+
>+#define IOM_DRAM_SDQS0 0x020e04bc
>+#define IOM_DRAM_SDQS1 0x020e04c0
>+#define IOM_DRAM_SDQS2 0x020e04c4
>+#define IOM_DRAM_SDQS3 0x020e04c8
>+#define IOM_DRAM_SDQS4 0x020e04cc
>+#define IOM_DRAM_SDQS5 0x020e04d0
>+#define IOM_DRAM_SDQS6 0x020e04d4
>+#define IOM_DRAM_SDQS7 0x020e04d8
>+
>+#define IOM_GRP_B0DS 0x020e0764
>+#define IOM_GRP_B1DS 0x020e0770
>+#define IOM_GRP_B2DS 0x020e0778
>+#define IOM_GRP_B3DS 0x020e077c
>+#define IOM_GRP_B4DS 0x020e0780
>+#define IOM_GRP_B5DS 0x020e0784
>+#define IOM_GRP_B6DS 0x020e078c
>+#define IOM_GRP_B7DS 0x020e0748
>+#define IOM_GRP_ADDDS 0x020e074c
>+#define IOM_DDRMODE_CTL 0x020e0750
>+#define IOM_GRP_DDRPKE 0x020e0754
>+#define IOM_GRP_DDRMODE 0x020e0760
>+#define IOM_GRP_CTLDS 0x020e076c
>+#define IOM_GRP_DDR_TYPE 0x020e0774
Ditto,
>+
>+#endif /*__ASM_ARCH_MX6S_DDR_H__ */
>diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
>b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
>new file mode 100644
>index 0000000..fcf304c
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
>@@ -0,0 +1,69 @@
>+/*
>+ * Copyright (C) 2012 Boundary Devices Inc.
Either 2013 or 2012 - 2013?
>+ *
>+ * This program is free software; you can redistribute it and/or modify
>+ * it under the terms of the GNU General Public License as published by
>+ * the Free Software Foundation; either version 2 of the License, or
>+ * (at your option) any later version.
>+
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+
>+ * You should have received a copy of the GNU General Public License
>+along
>+ * with this program; if not, write to the Free Software Foundation,
>+Inc.,
>+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>+ */
>+#ifndef __ASM_ARCH_MX6Q_DDR_H__
>+#define __ASM_ARCH_MX6Q_DDR_H__
>+
>+#ifndef CONFIG_MX6Q
>+#error "wrong CPU"
>+#endif
>+
>+#define IOM_DRAM_DQM0 0x020e05ac
>+#define IOM_DRAM_DQM1 0x020e05b4
>+#define IOM_DRAM_DQM2 0x020e0528
>+#define IOM_DRAM_DQM3 0x020e0520
>+#define IOM_DRAM_DQM4 0x020e0514
>+#define IOM_DRAM_DQM5 0x020e0510
>+#define IOM_DRAM_DQM6 0x020e05bc
>+#define IOM_DRAM_DQM7 0x020e05c4
>+
>+#define IOM_DRAM_CAS 0x020e056c
>+#define IOM_DRAM_RAS 0x020e0578
>+#define IOM_DRAM_RESET 0x020e057c
>+#define IOM_DRAM_SDCLK_0 0x020e0588
>+#define IOM_DRAM_SDCLK_1 0x020e0594
>+#define IOM_DRAM_SDBA2 0x020e058c
>+#define IOM_DRAM_SDCKE0 0x020e0590
>+#define IOM_DRAM_SDCKE1 0x020e0598
>+#define IOM_DRAM_SDODT0 0x020e059c
>+#define IOM_DRAM_SDODT1 0x020e05a0
>+
>+#define IOM_DRAM_SDQS0 0x020e05a8
>+#define IOM_DRAM_SDQS1 0x020e05b0
>+#define IOM_DRAM_SDQS2 0x020e0524
>+#define IOM_DRAM_SDQS3 0x020e051c
>+#define IOM_DRAM_SDQS4 0x020e0518
>+#define IOM_DRAM_SDQS5 0x020e050c
>+#define IOM_DRAM_SDQS6 0x020e05b8
>+#define IOM_DRAM_SDQS7 0x020e05c0
>+
>+#define IOM_GRP_B0DS 0x020e0784
>+#define IOM_GRP_B1DS 0x020e0788
>+#define IOM_GRP_B2DS 0x020e0794
>+#define IOM_GRP_B3DS 0x020e079c
>+#define IOM_GRP_B4DS 0x020e07a0
>+#define IOM_GRP_B5DS 0x020e07a4
>+#define IOM_GRP_B6DS 0x020e07a8
>+#define IOM_GRP_B7DS 0x020e0748
>+#define IOM_GRP_ADDDS 0x020e074c
>+#define IOM_DDRMODE_CTL 0x020e0750
>+#define IOM_GRP_DDRPKE 0x020e0758
>+#define IOM_GRP_DDRMODE 0x020e0774
>+#define IOM_GRP_CTLDS 0x020e078c
>+#define IOM_GRP_DDR_TYPE 0x020e0798
Ditto,
>+
>+#endif /*__ASM_ARCH_MX6Q_DDR_H__ */
>--
>1.7.9.5
>
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