[U-Boot] [PATCH] Add Boundary Devices Nitrogen6X boards

[Eric Nelson]

On 02/19/2013 01:52 PM, Benoît Thébaudeau wrote:
> Hi Eric,
>
> On Tuesday, February 19, 2013 9:20:48 PM, Eric Nelson wrote:
> [--snip--]
>> diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
>> b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
>> new file mode 100644
>> index 0000000..45b8879
>> --- /dev/null
>> +++ b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
> [--snip--]
>> +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
>> +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555B7974
>                                      ^A?
>> +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
>> +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
>> +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
>> +DATA 4, MX6_MMDC_P0_MDOR, 0x005B1023
>                                    ^A?
>> +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
>> +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
>> +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
>> +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
>> +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
>> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
>> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
>> +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
>> +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
>> +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
>> +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
>> +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
>> +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
>> +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
>> +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306
>> +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266
>> +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A
>> +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240
>> +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E
>> +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747
>> +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541
>> +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B
>> +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E
>> +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B
>> +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015
>> +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018
>> +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
>> +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
>> +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
>> +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
> [--snip--]
>
> tXS = tXPR = 170 ns -> 91 nCK -> 91 - 1 -> 0x5A.
>

Thanks Benoît,

I was going to bring this up in a separate thread.

While working through the details of our 800MHz
variants (Solo, Dual-Lite), and x256mx16 variants,
I re-worked these numbers and it seems that we
have an off-by-one issue with those fields.

According to the JEDEC spec and data sheets,
both tXS and tXPR should be 10nS greater than tRFC.

Since the nominal clock for i.MX6 is 528MHz (1.89nS),
this should be a delta of 6 clocks, not 5.

This change should apply to mx6q_4x_mt41j128.cfg as well.

There are some other things in that file that should
be fixed as well. The biggest among them is the settings
for P1_MPWLDECTRL0/1.

These settings are indicative of a fly-by topology,
which isn't used on SABRE Lite, and I don't think
is used on SABRE SD.

	DATA 4 0x021b480c 0x00440044
	DATA 4 0x021b4810 0x00440044

This was the primary thing that caused crashes
under stress on SABRE Lite and led to our flurry of
calibration tests as discussed here:

	http://boundarydevices.com/i-mx-6dq-u-boot-updates/

Should we take this up in a separate thread? It seems
un-related to our Nitrogen6X board.

Regards,


Eric