[U-Boot] [PATCH 1/4] sf: Add extended address register writing support

[Jagannadha Sutradharudu Teki]

This patch provides support to program a flash extended address
register.

extended/bank address register contains an information to access the
4th byte addressing in 3-byte address mode.

Currently added an extended/bank address register writing support for
spansion flashes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna at xilinx.com>
---
 drivers/mtd/spi/spi_flash.c          |   41 ++++++++++++++++++++++++++++++++++
 drivers/mtd/spi/spi_flash_internal.h |    6 +++++
 2 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 00aece9..232ccc0 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -269,6 +269,47 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
 	return 0;
 }
 
+int spi_flash_cmd_extaddr_write(struct spi_flash *flash, u8 ear)
+{
+	u8 cmd;
+	u8 idcode0;
+	int ret;
+
+	ret = spi_flash_cmd(flash->spi, CMD_READ_ID, &idcode0, 1);
+	if (ret) {
+		debug("SF: fail to read read id\n");
+		return ret;
+	}
+
+	if (idcode0 == 0x01)
+		cmd = CMD_EXT_BRWR;
+	else {
+		printf("SF: unable to support extaddr reg write"
+		" for %s flash\n", flash->name);
+		return -1;
+	}
+
+	ret = spi_flash_cmd_write_enable(flash);
+	if (ret < 0) {
+		debug("SF: enabling write failed\n");
+		return ret;
+	}
+
+	ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &ear, 1);
+	if (ret) {
+		debug("SF: fail to write ext addr register\n");
+		return ret;
+	}
+
+	ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+	if (ret < 0) {
+		debug("SF: write config register timed out\n");
+		return ret;
+	}
+
+	return 0;
+}
+
 /*
  * The following table holds all device probe functions
  *
diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h
index 141cfa8..dbceb81 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -28,6 +28,9 @@
 #define CMD_ERASE_64K			0xd8
 #define CMD_ERASE_CHIP			0xc7
 
+/* Extended addr acess commands */
+#define CMD_EXT_BRWR			0x17
+
 /* Common status */
 #define STATUS_WIP			0x01
 
@@ -77,6 +80,9 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 /* Program the status register. */
 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
 
+/* Program the extended address register */
+int spi_flash_cmd_extaddr_write(struct spi_flash *flash, u8 ear);
+
 /*
  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
  * bus. Used as common part of the ->read() operation.
-- 
1.7.4