[U-Boot] am33xx: fix the ddr_cmdtctrl structure

[Tom Rini]

On Mon, Jun 17, 2013 at 04:59:27PM +0300, Ilya Ledvich wrote:

> Fix the wrong mapping between the DDR I/O control registers on AM33XX
> SoCs and the software representation in the SPL code.
> The most recent public TRM defines the following DDR I/O control registers
> offsets:
>  * ddr_cmd0_ioctrl : offset 0x44E11404
>  * ddr_cmd1_ioctrl : offset 0x44E11408
>  * ddr_cmd2_ioctrl : offset 0x44E1140C
>  * ddr_data0_ioctrl: offset 0x44E11440
>  * ddr_data1_ioctrl: offset 0x44E11444
> 
> While the struct ddr_cmdtctrl has also some reserved bits in the beginning.
> The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points
> to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc.
> Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because
> of this mapping mismatch.
> 
> Signed-off-by: Ilya Ledvich <ilya at compulab.co.il>
> Reviewed-by: Peter Korsgaard <jacmet at sunsite.dk>

Applied to u-boot-ti/master, thanks!

-- 
Tom
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