[U-Boot] [PATCH 3/3] bootm: Add the missing PREP stage to bootz
Robert Nelson
robertcnelson at gmail.com
Wed Jul 3 16:46:30 CEST 2013
On Wed, Jul 3, 2013 at 9:12 AM, Simon Glass <sjg at chromium.org> wrote:
> In the recent bootm refactor, the PREP stage was missing in the bootz
> command. This causes unpredictable behaviour on platforms which need
> this stage to operate correctly (e.g. ARM).
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
> common/cmd_bootm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
> index 401055d..26ed7d8 100644
> --- a/common/cmd_bootm.c
> +++ b/common/cmd_bootm.c
> @@ -1794,7 +1794,8 @@ int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> bootm_disable_interrupts();
>
> ret = do_bootm_states(cmdtp, flag, argc, argv,
> - BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO,
> + BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO |
> + BOOTM_STATE_OS_GO,
> &images, 1);
>
> return ret;
> --
> 1.8.3
Still no dice.. v2013.07-rc2 + these 3 + Tom's "cmd_bootm.c: Correct
check/return for unsupported sub-command"
Tested with the Panda/Wand..
Panda: bootz test:
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Panda: bootm test: (this still works fine..)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} uImage
run mmcargs
bootm ${loadaddr}
U-Boot SPL 2013.07-rc2-00004-gb3e6fff-dirty (Jul 03 2013 - 09:33:36)
OMAP4430 ES2.1
OMAP SD/MMC: 0
reading u-boot.img
reading u-boot.img
U-Boot 2013.07-rc2-00004-gb3e6fff-dirty (Jul 03 2013 - 09:33:36)
CPU : OMAP4430 ES2.1
Board: OMAP4 Panda
I2C: ready
DRAM: 1 GiB
MMC: OMAP SD/MMC: 0
Using default environment
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 0
Panda # load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
reading zImage
3413152 bytes read in 160 ms (20.3 MiB/s)
Panda # run mmcargs
Panda # bootz ${loadaddr}
prefetch abort
pc : [<10da7a5c>] lr : [<bff813f1>]
sp : bfefdba0 ip : 7fe00fa8 fp : 00000000
r10: bfefe6a0 r9 : 00000002 r8 : bfefdf38
r7 : 80000000 r6 : 00000700 r5 : 10da7a5a r4 : bfefdc18
r3 : bfefdc18 r2 : bfefe6a0 r1 : 00000002 r0 : 00000100
Flags: NzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
Regards,
--
Robert Nelson
http://www.rcn-ee.com/
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