[U-Boot] [PATCH 4/4 V3] EXYNOS: Move files from board/samsung to arch/arm

[Minkyu Kang]

On 04/07/13 14:27, Rajeshwari Birje wrote:
> Hi Minkyu Kang,
> 
> On Thu, Jul 4, 2013 at 7:31 AM, Minkyu Kang <mk7.kang at samsung.com> wrote:
>>>>> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
>>>>> index 36b98c8..75dbe26 100644
>>>>> --- a/arch/arm/include/asm/arch-exynos/cpu.h
>>>>> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
>>>>> @@ -115,7 +115,7 @@
>>>>>  #define EXYNOS5_DMC_PHY0_BASE                0x10C00000
>>>>>  #define EXYNOS5_DMC_PHY1_BASE                0x10C10000
>>>>
>>>> maybe it can be dmc0 and dmc1
>>>> If you want to keep the interface with exynos4.
>>> EXYNOS4 donot have seperate Phy controller it is a part of  DMC controller.
>>> then I need to add following for EXYNOS4
>>> EXYNOS4_DMC_PHY1_BASE    DEVICE_NOT_AVAILABLE
>>> EXYNOS4_DMC_PHY_BASE       DEVICE_NOT_AVAILABLE
>>>
>>>>
>>>>>  #define EXYNOS5_GPIO_PART3_BASE              0x10D10000
>>>>> -#define EXYNOS5_DMC_CTRL_BASE                0x10DD0000
>>>>> +#define EXYNOS5_DMC0_BASE            0x10DD0000
>>>>
>>>> why?
>>> if we want to make funstion to get the DMC base address it is needed
>>> to be added for EXYNOS5 as well
>>> hence made this change.
>>>>
>>>>>  #define EXYNOS5_GPIO_PART1_BASE              0x11400000
>>>>>  #define EXYNOS5_MIPI_DSIM_BASE               0x11D00000
>>>>>  #define EXYNOS5_USB_HOST_EHCI_BASE   0x12110000
>>>>> @@ -135,6 +135,7 @@
>>>>>
>>>>>  #define EXYNOS5_ADC_BASE             DEVICE_NOT_AVAILABLE
>>>>>  #define EXYNOS5_MODEM_BASE           DEVICE_NOT_AVAILABLE
>>>>> +#define EXYNOS5_DMC1_BASE            DEVICE_NOT_AVAILABLE
>>>>
>>>> It looks weird.
>>> Since EXYNOS4 has 2 DMC controllers and EXYNOS5 has only 1 DMC
>>> controller I had to add this to avoid compilation error.
>>> Please do let me know if  you are fine with these changes.
>>>>
>>
>> I suggest following.
> Needed a clarification:
>>
>> EXYNOS4_DMC_BASE        0x-
>> EXYNOS4_DMC_PHY_BASE    DEVICE_NOT_AVAILABLE
> But we have 2 DMC controller DMC0 and DMC1
> so it will be  EXYNOS4_DMC0_BASE and  EXYNOS4_DMC1_BASE
> EXYNOS4_DMC1_BASE not available in EXYNOS5

no.
It means.. DO NOT define dmc0 and dmc1 separately.
We need dmc base and we can access  dmc1.
For example, uart have 4 devices but we defined uart0 address as UART's base.
and access by offset.

	u32 offset = dev_index * sizeof(struct s5p_uart);
	return (struct s5p_uart *)(samsung_get_base_uart() + offset);


>>
>> EXYNOS4X12_DMC_BASE     0x-
>> EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
>>
>> EXYNOS5_DMC_PHY_BASE    0x-
> It has 2 phy controllers so it would be EXYNOS5_DMC_PHY0_BASE and
> EXYNOS5_DMC_PHY1_BASE and it would be DEVICE_NOT_AVAILABLE in other 2
> SOC

no.

> 
>> EXYNOS5_DMC_BASE        0x-
>>
>> then we need to add 2 SAMSUNG_BASE.
>>
>> SAMSUNG_BASE(dmc, DMC_BASE)
>> SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
>>
>> and we can access dmc1 and dmc phy1 by offset.
>>
>> What do you think about it?
>>
>> Thanks,
>> Minkyu Kang.