[U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

[Fabio Estevam]

Hi Tom,

On Fri, Jul 19, 2013 at 6:50 PM, Tom Rini <trini at ti.com> wrote:
> On Fri, Jul 19, 2013 at 02:34:55PM -0700, Troy Kisky wrote:
>> On 7/19/2013 2:00 PM, Fabio Estevam wrote:
>> >Hi Troy,
>> >
>> >On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky
>> ><troy.kisky at boundarydevices.com> wrote:
>> >>The old value of 0x000e0030 will cause ethernet
>> >>timeout issues on the sabrelite and possibly other
>> >>boards using the KSZ9021.
>> >>I have no explanation as to why.
>> >>
>> >>But this is a correct change, the TRM will be updated
>> >>to show that 00b is the only valid setting for bits
>> >>19-18 of DRAM_RESET.
>> >>
>> >>My thanks go to Liu Hui(Jason) for this information.
>> >>
>> >>Signed-off-by: Troy Kisky <troy.kisky at boundarydevices.com>
>> >Should this go into 2013.07?
>> >
>>
>> If not too late. It only affect Nitrogen6x, at least until Sabrelite
>> is combined with it.
>> And Sabrelite is already using this value.
>
> Whose acks should I wait for on this?

Just realized I acked in the original message and you were not on Cc, so

Acked-by: Fabio Estevam <fabio.estevam at freescale.com>

As Jason Liu explained the mx6 reference manual will be updated to fix
the incorrect setting.

Thanks,

Fabio Estevam