[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Andreas Bießmann]

Hi all,

was on vacation, so answering late.

On 19.07.13 14:13, Tom Rini wrote:
> On Wed, Jul 17, 2013 at 05:14:17PM +0800, Bo Shen wrote:
> 
>> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
>> and share the lower 8 bits data line. If use low drive of the data
>> line, it will cause DDR data access corrupt in lower address, so
>> change the data line to high drive mode
>>
>> This will fix the Linux kernel boot issue when use Lower address
>>
>> Signed-off-by: Bo Shen <voice.shen at atmel.com>
>> ---
>>  board/atmel/at91sam9n12ek/at91sam9n12ek.c |    2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
>> index 3013a42..66c4c1f 100644
>> --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
>> +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
>> @@ -59,7 +59,7 @@ static void at91sam9n12ek_nand_hw_init(void)
>>  	/* Configure databus */
>>  	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
>>  	/* Configure IO drive */
>> -	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
>> +	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
>>  
>>  	writel(csa, &matrix->ebicsa);
>>  
> 
> So, the change is small and isolated, so I'm OK applying it to master
> directly, once we've got acks.  But it sounds like there's a question of
> "why does this fix the problem" and "how does the problem even happen?".

Well, you have to know that the at91sam9n12 SoC is relatively new and
introduced alongside the at91sam9n12-ek board by
9e336903891f1c28be04f0b5503ca54939b2976a in this releases MW. The
question "how does the problem even happen" could therefore possibly
answered with "not enough testing before sending the patch".
I can't say much about that, cause I have no access to such a board and
have to rely on Bo's and Josh's input. So when Bo says it fixes a real
bug I believe in it.

To answer the second question we can have a look at the specs. I can
presume by looking at the specs that we need to switch the drive
strength for the data I/O pins to higher level for this board to fix the
problem mentioned in the commit message. You have to know that this
specific part (configuring EBI for NAND access) is copied from board to
board (yes, another point to consolidate in near future). And this
specific part is copied over from at91samx5ek which seems to work with
lower drive strength. Unfortunately the concrete limit of EBI
capacitance is not specified in specs for at91sam9n12 nor at91sam9x35
devices. More distracting this parameter (EBI_DRIVE) seems to have
different reset values in at91sam9n12 and atsam9x35 devices, at least
the specs say so ... Atmel guys, please have a look on that and update
your specs!
Especially fill the TBD field in at91sam9n12 spec p. 311 (EBI_DRIVE in
CCFG_EBICSA) in version 11063I–ATARM–17-Apr-13. And possibly check why
there is EBI_DRIVE default to 'low' for 9x5 and default to 'high' for
9n12. There is also another bug in the specs, when you have to decide
between 'high' and 'low' you cant say the 'low' is required for
'capacitance < TBD pF' and 'high' is required for 'capacitance < TBD
pF', presumably the 'high' part should be chosen for 'capacitance > TBD pF'.

So from my point of view this patch fixes an existing bug in a new board
introduced in this releases MW. It uses a fairly new SoC which is first
used in this new board. Therefore

Acked-by: Andreas Bießmann <andreas.devel at googlemail.com>

And Tom, please apply this patch directly.

Best regards

Andreas Bießmann