[U-Boot] [PATCH] Tegra114: Fix/update GP padcfg register struct

Tom Warren TWarren at nvidia.com
Thu Mar 14 03:13:06 CET 2013


Stephen,

> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Wednesday, March 13, 2013 4:30 PM
> To: Tom Warren
> Cc: u-boot at lists.denx.de; Stephen Warren; Tom Warren
> Subject: Re: [U-Boot] [PATCH] Tegra114: Fix/update GP padcfg register struct
> 
> On 03/13/2013 04:34 PM, Tom Warren wrote:
> > Differences in padcfg registers (some removed, some added) between
> > Tegra30 and Tegra114 weren't picked up when I ported this file.
> > Also removed the HSM setting for SDIOCFG - not called out in TRM.
> 
> The actual diff would be a lot easier to see if the register offsets hadn't all
> had 0x800 added to them as well in the same patch. MODEREG and HIDREV
> are at the same absolute address in Tegra20/30/114 for example.
I felt it prudent to add 0x800 since the register addresses spilled over into the 0x900 range, and it would have looked weird to have 0xFC, then 0x900, 0x904, etc.
I could revert the old offset, and then make the change to the new regs go 0xFC, then 0x100, 0x104, etc. i.e. offset based off of the absolute address of the GP base of 0x70000800. Let me know.

Tom

> 
> I didn't check the content of this patch due to that, but it seems fine if it
> matches the TRM.
--
nvpublic



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