[U-Boot] [PATCH v2 3/7] cros: add SPI support for cros_ec
Hung-ying Tyan
tyanh at chromium.org
Mon Mar 18 17:22:03 CET 2013
This patch adds SPI support for carrying out the cros_ec protocol.
Signed-off-by: Hung-ying Tyan <tyanh at chromium.org>
Signed-off-by: Randall Spangler <rspangler at chromium.org>
Signed-off-by: Simon Glass <sjg at chromium.org>
---
Changes in v2:
- Wrapped lines to comply with the 80-char rule.
drivers/misc/Makefile | 1 +
drivers/misc/cros_ec_spi.c | 166 +++++++++++++++++++++++++++++++++++++++++++++
drivers/spi/exynos_spi.c | 22 ++++++
include/spi.h | 16 +++++
4 files changed, 205 insertions(+)
create mode 100644 drivers/misc/cros_ec_spi.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 9363ef9..18209ec 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
COBJS-$(CONFIG_CROS_EC) += cros_ec.o
COBJS-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
+COBJS-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
new file mode 100644
index 0000000..82cc1bb
--- /dev/null
+++ b/drivers/misc/cros_ec_spi.c
@@ -0,0 +1,166 @@
+/*
+ * Chromium OS cros_ec driver - SPI interface
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * The Matrix Keyboard Protocol driver handles talking to the keyboard
+ * controller chip. Mostly this is for keyboard functions, but some other
+ * things have slipped in, so we provide generic services to talk to the
+ * KBC.
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <spi.h>
+
+#ifdef CONFIG_NEW_SPI_XFER
+#error "CONFIG_NEW_SPI_XFER not supported in CROS_EC"
+#endif
+
+/**
+ * Send a command to a LPC CROS_EC device and return the reply.
+ *
+ * The device's internal input/output buffers are used.
+ *
+ * @param dev CROS_EC device
+ * @param cmd Command to send (EC_CMD_...)
+ * @param cmd_version Version of command to send (EC_VER_...)
+ * @param dout Output data (may be NULL If dout_len=0)
+ * @param dout_len Size of output data in bytes
+ * @param dinp Returns pointer to response data. This will be
+ * untouched unless we return a value > 0.
+ * @param din_len Maximum size of response in bytes
+ * @return number of bytes in response, or -1 on error
+ */
+int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
+ const uint8_t *dout, int dout_len,
+ uint8_t **dinp, int din_len)
+{
+ int in_bytes = din_len + 4; /* status, length, checksum, trailer */
+ uint8_t *out;
+ uint8_t *p;
+ int csum, len;
+ int rv;
+
+ /*
+ * Sanity-check input size to make sure it plus transaction overhead
+ * fits in the internal device buffer.
+ */
+ if (in_bytes > sizeof(dev->din)) {
+ debug("%s: Cannot receive %d bytes\n", __func__, din_len);
+ return -1;
+ }
+
+ /* We represent message length as a byte */
+ if (dout_len > 0xff) {
+ debug("%s: Cannot send %d bytes\n", __func__, dout_len);
+ return -1;
+ }
+
+ /*
+ * TODO(sjg at chromium.org): Clear input buffer so we don't get false
+ * hits for MSG_HEADER
+ */
+ memset(dev->din, '\0', in_bytes);
+
+ if (spi_claim_bus(dev->spi)) {
+ debug("%s: Cannot claim SPI bus\n", __func__);
+ return -1;
+ }
+
+ out = dev->dout;
+ out[0] = cmd_version;
+ out[1] = cmd;
+ out[2] = (uint8_t)dout_len;
+ memcpy(out + 3, dout, dout_len);
+ csum = cros_ec_calc_checksum(out, 3)
+ + cros_ec_calc_checksum(dout, dout_len);
+ out[3 + dout_len] = (uint8_t)csum;
+
+ /*
+ * Send output data and receive input data starting such that the
+ * message body will be dword aligned.
+ */
+ p = dev->din + sizeof(int64_t) - 2;
+ len = dout_len + 4;
+ cros_ec_dump_data("out", cmd, out, len);
+ rv = spi_xfer(dev->spi, max(len, in_bytes) * 8, out, p,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ spi_release_bus(dev->spi);
+
+ if (rv) {
+ debug("%s: Cannot complete SPI transfer\n", __func__);
+ return -1;
+ }
+
+ len = min(p[1], din_len);
+ cros_ec_dump_data("in", -1, p, len + 3);
+
+ /* Response code is first byte of message */
+ if (p[0] != EC_RES_SUCCESS) {
+ printf("%s: Returned status %d\n", __func__, p[0]);
+ return -(int)(p[0]);
+ }
+
+ /* Check checksum */
+ csum = cros_ec_calc_checksum(p, len + 2);
+ if (csum != p[len + 2]) {
+ debug("%s: Invalid checksum rx %#02x, calced %#02x\n", __func__,
+ p[2 + len], csum);
+ return -1;
+ }
+
+ /* Anything else is the response data */
+ *dinp = p + 2;
+
+ return len;
+}
+
+int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
+{
+ /* Decode interface-specific FDT params */
+ dev->max_frequency = fdtdec_get_int(blob, dev->node,
+ "spi-max-frequency", 500000);
+ dev->cs = fdtdec_get_int(blob, dev->node, "reg", 0);
+
+ return 0;
+}
+
+/**
+ * Initialize SPI protocol.
+ *
+ * @param dev CROS_EC device
+ * @param blob Device tree blob
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
+{
+ dev->spi = spi_setup_slave_fdt(blob, dev->parent_node,
+ dev->cs, dev->max_frequency, 0);
+ if (!dev->spi) {
+ debug("%s: Could not setup SPI slave\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index be60ada..23c5a00 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -416,6 +416,28 @@ static int process_nodes(const void *blob, int node_list[], int count)
return 0;
}
+/**
+ * Set up a new SPI slave for an fdt node
+ *
+ * @param blob Device tree blob
+ * @param node SPI peripheral node to use
+ * @return 0 if ok, -1 on error
+ */
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
+ unsigned int cs, unsigned int max_hz, unsigned int mode)
+{
+ struct spi_bus *bus;
+ unsigned int i;
+
+ for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
+ if (bus->node == node)
+ return spi_setup_slave(i, cs, max_hz, mode);
+ }
+
+ debug("%s: Failed to find bus node %d\n", __func__, node);
+ return NULL;
+}
+
/* Sadly there is no error return from this function */
void spi_init(void)
{
diff --git a/include/spi.h b/include/spi.h
index 60e85db..cfcb140 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -198,4 +198,20 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
return ret < 0 ? ret : din[1];
}
+/**
+ * Set up a SPI slave for a particular device tree node
+ *
+ * This calls spi_setup_slave() with the correct bus number. Call
+ * spi_free_slave() to free it later.
+ *
+ * @param blob Device tree blob
+ * @param node SPI peripheral node to use
+ * @param cs Chip select to use
+ * @param max_hz Maximum SCK rate in Hz (0 for default)
+ * @param mode Clock polarity, clock phase and other parameters
+ * @return pointer to new spi_slave structure
+ */
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
+ unsigned int cs, unsigned int max_hz, unsigned int mode);
+
#endif /* _SPI_H_ */
--
1.8.1.3
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