[U-Boot] [PATCH] powerpc/corenet: Add workaround for ELBC multi-bit ECC error

[Shaohui Xie]

NAND operations in condition like below will result ELBC internal multi-bit
ECC error, DCFG will send this error to MPIC to report it as an error
interrupt (Interrupt 0), which causes call trace in kernel, so software
should disable the DCFG not to send the ELBC ECC error by setting bit 15
in the register at DCSRBASE + 0x0002_0520. This won't inhibit the reporting
of LTESR[PAR]. This workaround is enabled on P2041/P3041/P50x0.

steps to reproduce the issue:
1. power cycle the board
2. use following command to do NAND test:
flashcp -v file-jffs2 /dev/mtdx

The 'mtdx' should be a NAND partition, the file 'file-jffs2' should be
page aligned.

Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
---
Sorry! 
I have to resent since I still cannot find the patch in patch work.

 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |  3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       | 10 ++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h |  4 ++++
 3 files changed, 17 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5d72f4c..671c205 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -227,6 +227,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 	puts("Work-around for Erratum NMG_LBC103 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+	puts("Work-around for Erratum ELBC MULTIBIT ECC enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index de9d916..c43be5e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -592,6 +592,16 @@ skip_l2:
 		}
 	}
 #endif
+#ifdef CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+	/*
+	 * On P2041/P3041/P50x0, NAND operations will result internal multi-bit
+	 * ECC error, which causes call trace in kernel, so software should
+	 * disable the ECC error reported from eLBC by setting bit 15 in
+	 * the register at DCSRBASE + 0x0002_0520.
+	 */
+#define DCFG_ECC	(CONFIG_SYS_DCSRBAR + 0x20520)
+	setbits_be32((void *)DCFG_ECC, 1 << (31 - 15));
+#endif
 
 #ifdef CONFIG_SYS_LBC_LCRR
 	/*
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d57c178..926316d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -345,6 +345,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -377,6 +378,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -451,6 +453,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_PPC_P5040)
 #define CONFIG_SYS_PPC64
@@ -480,6 +483,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS			1
-- 
1.8.0