[U-Boot] [PATCH] mmc: mx6qsabrelite: fsl_esdhc: Define maximum bus width supported by SabreLite board

[Abbas Raza]

From: Abbas Raza <Abbas_Raza at mentor.com>

Maximum bus width supported by SabreLite board is not 8bit like
all other mx6q specific boards. In case where both host controller
and card support 8bit transfers, they agree to communicate on 8bit
interface while boards like the SabreLite support only 4bit interface.
Due to this reason the mmc 8bit default mode fails on the SabreLite.
To rectify this, define maximum bus width supported by this board (4bit).
If max_bus_width is not defined, it is 0 by default and 8bit width support
will be enabled in host capabilities otherwise host capabilities are modified
accordingly.

It is tested with a MMCplus card.

Signed-off-by: Abbas Raza <Abbas_Raza at mentor.com>
cc: stefano Babic <sbabic at denx.de>
cc: Andy Fleming <afleming at gmail.com>
Acked-by: Dirk Behme <dirk.behme at de.bosch.com>
Acked-by: Andrew Gabbasov <andrew_gabbasov at mentor.com>
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c | 3 +++
 drivers/mmc/fsl_esdhc.c                       | 7 +++++++
 include/fsl_esdhc.h                           | 1 +
 3 files changed, 11 insertions(+)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index d563464..14c299b 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -110,6 +110,9 @@ int board_mmc_init(bd_t *bis)
 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 
+	usdhc_cfg[0].max_bus_width = 4;
+	usdhc_cfg[1].max_bus_width = 4;
+
 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index)
 		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3d5c9c0..d2a505e 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -579,6 +579,13 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 
 	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 
+	if (cfg->max_bus_width > 0) {
+		if (cfg->max_bus_width < 8)
+			mmc->host_caps &= ~MMC_MODE_8BIT;
+		if (cfg->max_bus_width < 4)
+			mmc->host_caps &= ~MMC_MODE_4BIT;
+	}
+
 	if (caps & ESDHC_HOSTCAPBLT_HSS)
 		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 47d2fe4..0a1a071 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -168,6 +168,7 @@
 struct fsl_esdhc_cfg {
 	u32	esdhc_base;
 	u32	sdhc_clk;
+	u8	max_bus_width;
 };
 
 /* Select the correct accessors depending on endianess */
-- 
1.8.2