[U-Boot] [PATCH 11/23] powerpc/t4240qds: Update DDR timing table

[Wolfgang Denk]

Dear York Sun,

In message <1363972531-25641-11-git-send-email-yorksun at freescale.com> you wrote:
> Update the timing table to support more rank density, based on the theory
> that similar density DIMMs have similar clock adjust and write level start
> timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
> MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.
> 
> Signed-off-by: York Sun <yorksun at freescale.com>
> ---
>  board/freescale/t4qds/ddr.c |   56 ++++++++++++++++++++++++++-----------------
>  1 file changed, 34 insertions(+), 22 deletions(-)

CHECK: Alignment should match open parenthesis
#194: FILE: board/freescale/t4qds/ddr.c:121:
+               if (pbsp->n_ranks == pdimm->n_ranks &&
+                  (pdimm->rank_density >> 30) >= pbsp->rank_gb) {



Best regards,

Wolfgang Denk

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