[U-Boot] [PATCH 15/23] T4/USB: Add USB 2.0 UTMI dual phy support

[Wolfgang Denk]

Dear York Sun,

In message <1363972531-25641-15-git-send-email-yorksun at freescale.com> you wrote:
> From: Roy Zang <tie-fei.zang at freescale.com>
> 
> T4240 internal UTMI phy is different comparing to previous UTMI PHY
> in P3041.
> This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
> T4240.
> The phy timing is very sensitive and moving the phy enable code to
> cpu_init.c will not work.
> 
> Signed-off-by: Roy Zang <tie-fei.zang at freescale.com>
> ---
>  arch/powerpc/include/asm/config_mpc85xx.h |    3 +--
>  arch/powerpc/include/asm/immap_85xx.h     |   41 +++++++++++++++++++++++++++++
>  drivers/usb/host/ehci-fsl.c               |   21 +++++++++++++++
>  3 files changed, 63 insertions(+), 2 deletions(-)

WARNING: do not add new typedefs
#144: FILE: arch/powerpc/include/asm/immap_85xx.h:2832:
+typedef struct ccsr_usb_port_ctrl {

WARNING: do not add new typedefs
#161: FILE: arch/powerpc/include/asm/immap_85xx.h:2849:
+typedef struct ccsr_usb_phy {

CHECK: Alignment should match open parenthesis
#205: FILE: drivers/usb/host/ehci-fsl.c:96:
+               setbits_be32(&usb_phy->pllprg[1],
+                               CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |

CHECK: Alignment should match open parenthesis
#210: FILE: drivers/usb/host/ehci-fsl.c:101:
+               setbits_be32(&usb_phy->port1.ctrl,
+                               CONFIG_SYS_FSL_USB_CTRL_PHY_EN);

CHECK: Alignment should match open parenthesis
#212: FILE: drivers/usb/host/ehci-fsl.c:103:
+               setbits_be32(&usb_phy->port1.drvvbuscfg,
+                               CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);

CHECK: Alignment should match open parenthesis
#214: FILE: drivers/usb/host/ehci-fsl.c:105:
+               setbits_be32(&usb_phy->port1.pwrfltcfg,
+                               CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);

CHECK: Alignment should match open parenthesis
#216: FILE: drivers/usb/host/ehci-fsl.c:107:
+               setbits_be32(&usb_phy->port2.ctrl,
+                               CONFIG_SYS_FSL_USB_CTRL_PHY_EN);

CHECK: Alignment should match open parenthesis
#218: FILE: drivers/usb/host/ehci-fsl.c:109:
+               setbits_be32(&usb_phy->port2.drvvbuscfg,
+                               CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);

CHECK: Alignment should match open parenthesis
#220: FILE: drivers/usb/host/ehci-fsl.c:111:
+               setbits_be32(&usb_phy->port2.pwrfltcfg,
+                               CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);


Best regards,

Wolfgang Denk

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