[U-Boot] [PATCH 14/21] powerpc/b4860qds: Assign DDR address in board file

[Wolfgang Denk]

Dear York Sun,

In message <1363973052-25918-12-git-send-email-yorksun at freescale.com> you wrote:
> B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
> This is the requirement for DSP cores to run in 32-bit address space.
> 
> Signed-off-by: York Sun <yorksun at freescale.com>
> ---
>  board/freescale/b4860qds/ddr.c |   72 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)

CHECK: Alignment should match open parenthesis
#151: FILE: board/freescale/b4860qds/ddr.c:213:
+               debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
+                       rank_density, ctlr_density);

WARNING: line over 80 characters
#153: FILE: board/freescale/b4860qds/ddr.c:215:
+                       switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {

CHECK: Alignment should match open parenthesis
#187: FILE: board/freescale/b4860qds/ddr.c:249:
+                               debug("ctrl %d dimm %d base 0x%llx\n",
+                                       i, j, current_mem_base);


Best regards,

Wolfgang Denk

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