[U-Boot] [Patch v2, batch 4 02/29] Enable L2 cache parity/ECC error checking
York Sun
yorksun at freescale.com
Mon Mar 25 18:39:58 CET 2013
From: James Yang <James.Yang at freescale.com>
Enable L2 cache parity/ECC error checking.
Signed-off-by: James Yang <James.Yang at freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +-
arch/powerpc/cpu/mpc85xx/start.S | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d61791a..f697c3d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -337,7 +337,7 @@ int enable_cluster_l2(void)
while ((in_be32(&l2cache->l2csr0)
& (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
;
- out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+ out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE);
}
i++;
} while (!(cluster & TP_CLUSTER_EOC));
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 5542d0a..87168e2 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -734,7 +734,7 @@ enable_l2_cluster_l2:
isync
and. r1, r0, r4
bne 1b
- lis r4, L2CSR0_L2E at h
+ lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
sync
stw r4, 0(r3) /* enable L2 */
delete_ccsr_l2_tlb:
--
1.7.9.5
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