[U-Boot] [Patch v2, batch 4 12/29] powerpc/mpc8xxx: Allow DDR overclock

[York Sun]

Allow DDR clock runs faster than SPD specifes. This may cause memory
failure, but the user should know what is going to happen when using
higher than expected DDR clock.

Signed-off-by: Ed Swarthout <Ed.Swarthout at freescale.com>
Signed-off-by: York Sun <yorksun at freescale.com>
---
 .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c        |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 9adde31..e958e13 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -44,7 +44,6 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 		printf("DDR clock (MCLK cycle %u ps) is faster than "
 			"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
 			mclk_ps, tCKmin_X_ps);
-		return 1;
 	}
 	/* determine the acutal cas latency */
 	caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
@@ -60,7 +59,6 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 	if (caslat_actual * mclk_ps > 20000) {
 		printf("The choosen cas latency %d is too large\n",
 			caslat_actual);
-		return 1;
 	}
 	outpdimm->lowest_common_SPD_caslat = caslat_actual;
 
-- 
1.7.9.5