[U-Boot] [PATCH 4/8] Add TI816X ddr definitions
TENART Antoine
atenart at adeneo-embedded.com
Thu Mar 28 18:14:37 CET 2013
---
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 4 +
arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h | 250 ++++++++++++++++++++
2 files changed, 254 insertions(+)
create mode 100644 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 15ca4c1..b959ba8 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -22,6 +22,10 @@
#include <asm/arch/hardware.h>
#include <asm/emif.h>
+#if defined(CONFIG_TI816X)
+#include <asm/arch/ddr_defs_ti816x.h>
+#endif
+
/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h b/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
new file mode 100644
index 0000000..0853d7f
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
@@ -0,0 +1,250 @@
+/*
+ * ddr_defs_ti816x.h
+ *
+ * ddr specific header for TI816X
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart at adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _DDR_DEFS_TI816X_H
+#define _DDR_DEFS_TI816X_H
+
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_TI816X_EVM_DDR3
+
+#define CONFIG_TI816X_DDR3_796 /* Values supported 400,531,675,796 */
+#define CONFIG_TI816X_DDR3_SW_LEVELING /* Enable software leveling as part of DDR3 init*/
+
+/*
+ * DDR3 force values. These are board dependent
+ */
+
+/* EVM 400 MHz clock Settings
+ * EVM has only a single RANK (chip select) */
+#define N_RANK 1
+
+/*
+ * Invert clock adds an additional half cycle delay on the command
+ * interface. The additional half cycle, is usually meant to enable
+ * leveling in the situation that DQS is later than CK on the board. It
+ * also helps provide some additional margin for leveling.
+ *
+ * For the EVM this is helping us with additional room for the write
+ * leveling. Since the dqs delays are very small.
+ */
+#define INVERT_CLOCK 1
+
+/*
+ * CMD_SLAVE_RATIO determines where is the command placed with respect
+ * to the clock edge. This is a ratio, implying 0x100 is one cycle.
+ * Ideally the command is centered so - this should be half cycle
+ * delay (0x80). But if invert clock is in use, an additional half
+ * cycle must be added
+ */
+#define CMD_SLAVE_FROM_INV_CLOCK(i) (((i) == 0) ? 0x80 : 0x100)
+#define CMD_SLAVE_RATIO CMD_SLAVE_FROM_INV_CLOCK(INVERT_CLOCK)
+
+/*
+ * This represents the initial value for the leveling process. The
+ * value is a ratio - so 0x100 represents one cycle. The real delay
+ * is determined through the leveling process.
+ *
+ * During the leveling process, 0x20 is subtracted from the value, so
+ * we have added that to the value we want to set. We also set the
+ * values such that byte3 completes leveling after byte2 and byte1
+ * after byte0.
+ */
+#define WR_DQS_RATIO_0 0x20
+#define WR_DQS_RATIO_1 0x20
+#define WR_DQS_RATIO_2 0x20
+#define WR_DQS_RATIO_3 0x20
+
+/*
+ * This represents the initial value for the leveling process. The
+ * value is a ratio - so 0x100 represents one cycle. The real delay
+ * is determined through the leveling process.
+ *
+ * During the leveling process, 0x20 is subtracted from the value, so
+ * we have added that to the value we want to set. We also set the
+ * values such that byte3 completes leveling after byte2 and byte1
+ * after byte0.
+ */
+#define RD_GATE_RATIO_0 0x20
+#define RD_GATE_RATIO_1 0x20
+#define RD_GATE_RATIO_2 0x20
+#define RD_GATE_RATIO_3 0x20
+
+/*
+ * data rate in MHz. The DDR clock will be 1/2 of this value
+ */
+#define DDR_DATA_RATE 800
+
+#define USE_EMIF0 1
+#define USE_EMIF1 1
+
+/*
+ * EMIF Paramters. Refer the EMIF register documentation and the
+ * memory datasheet for details
+ */
+/* For 400 MHz */
+#if defined(CONFIG_TI816X_DDR3_400)
+#define EMIF_TIM1 0x0CCCE524
+#define EMIF_TIM2 0x30308023
+#define EMIF_TIM3 0x009F82CF
+#define EMIF_SDREF 0x10000C30
+#define EMIF_SDCFG 0x62A41032
+#define EMIF_PHYCFG 0x0000010B
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE 0x12A
+#define RD_DQS 0x3B
+#define WR_DQS 0xA6
+#endif
+
+#endif /* CONFIG_TI816X_DDR3_400 */
+
+/* For 531 MHz */
+#if defined(CONFIG_TI816X_DDR3_531)
+#define EMIF_TIM1 0x0EF136AC
+#define EMIF_TIM2 0x30408063
+#define EMIF_TIM3 0x009F83AF
+#define EMIF_SDREF 0x1000102E
+#define EMIF_SDCFG 0x62A51832
+#define EMIF_PHYCFG 0x0000010C
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE 0x13D
+#define RD_DQS 0x39
+#define WR_DQS 0xB4
+#endif
+
+#endif /* CONFIG_TI816X_DDR_531 */
+
+/* For 675 MHz */
+#if defined(CONFIG_TI816X_DDR3_675)
+#define EMIF_TIM1 0x13358875
+#define EMIF_TIM2 0x5051806C
+#define EMIF_TIM3 0x009F84AF
+#define EMIF_SDREF 0x10001491
+#define EMIF_SDCFG 0x62A63032
+#define EMIF_PHYCFG 0x0000010F
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE 0x196
+#define RD_DQS 0x39
+#define WR_DQS 0x91
+
+#endif
+
+#endif /* CONFIG_TI816X_DDR3_675 */
+
+/* For 796 MHz */
+#if defined(CONFIG_TI816X_DDR3_796)
+#define EMIF_TIM1 0x1779C9FE
+#define EMIF_TIM2 0x50608074
+#define EMIF_TIM3 0x009F857F
+#define EMIF_SDREF 0x10001841
+#define EMIF_SDCFG 0x62A73832
+#define EMIF_PHYCFG 0x00000110
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE 0x1B3
+#define RD_DQS 0x35
+#define WR_DQS 0x93
+
+#endif
+
+#endif /* CONFIG_TI816X_DDR_796 */
+
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+#define WR_DQS_RATIO_BYTE_LANE3 ((WR_DQS << 10) | WR_DQS)
+#define WR_DQS_RATIO_BYTE_LANE2 ((WR_DQS << 10) | WR_DQS)
+#define WR_DQS_RATIO_BYTE_LANE1 ((WR_DQS << 10) | WR_DQS)
+#define WR_DQS_RATIO_BYTE_LANE0 ((WR_DQS << 10) | WR_DQS)
+
+#define WR_DATA_RATIO_BYTE_LANE3 (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE2 (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE1 (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE0 (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
+
+#define RD_DQS_RATIO ((RD_DQS << 10) | RD_DQS)
+
+#define DQS_GATE_BYTE_LANE0 ((RD_DQS_GATE << 10) | RD_DQS_GATE)
+#define DQS_GATE_BYTE_LANE1 ((RD_DQS_GATE << 10) | RD_DQS_GATE)
+#define DQS_GATE_BYTE_LANE2 ((RD_DQS_GATE << 10) | RD_DQS_GATE)
+#define DQS_GATE_BYTE_LANE3 ((RD_DQS_GATE << 10) | RD_DQS_GATE)
+
+#endif /* CONFIG_TI816X_DDR3_SW_LEVELING */
+
+#endif /* CONFIG_TI816X_EVM_DDR3 */
+
+#ifdef CONFIG_TI816X_EVM_DDR2
+
+#define INVERT_CLK_OUT 0x0
+#define CMD_SLAVE_RATIO 0x80
+/*
+ * DDR2 ratio values. These are board dependent
+ * obtained from sweep experiments
+ */
+
+/* EVM 400 MHz clock Settings */
+
+#define WR_DQS_RATIO_BYTE_LANE3 ((0x4a << 10) | 0x4a)
+#define WR_DQS_RATIO_BYTE_LANE2 ((0x4a << 10) | 0x4a)
+#define WR_DQS_RATIO_BYTE_LANE1 ((0x4a << 10) | 0x4a)
+#define WR_DQS_RATIO_BYTE_LANE0 ((0x4a << 10) | 0x4a)
+
+#define WR_DATA_RATIO_BYTE_LANE3 (((0x4a + 0x40) << 10) | (0x4a + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE2 (((0x4a + 0x40) << 10) | (0x4a + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE1 (((0x4a + 0x40) << 10) | (0x4a + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE0 (((0x4a + 0x40) << 10) | (0x4a + 0x40))
+
+#define RD_DQS_RATIO ((0x40 << 10) | 0x40)
+
+#define DQS_GATE_BYTE_LANE0 ((0x13a << 10) | 0x13a)
+#define DQS_GATE_BYTE_LANE1 ((0x13a << 10) | 0x13a)
+#define DQS_GATE_BYTE_LANE2 ((0x13a << 10) | 0x13a)
+#define DQS_GATE_BYTE_LANE3 ((0x13a << 10) | 0x13a)
+
+/*
+ * EMIF Paramters
+ */
+#define EMIF_TIM1 0xAAB15E2
+#define EMIF_TIM2 0x423631D2
+#define EMIF_TIM3 0x80032F
+#define EMIF_SDREF 0x10000C30
+#define EMIF_SDCFG 0x43801A3A /* 32 bit ddr2, CL=6, CWL=5, 13 rows, 8 banks, 10 bit column, 2 CS */
+/*
+ * TI816x PG1.0 EMIF_PHYCFG 0x0000030B local odt = 3, read latency = 11
+ * TI816x PG1.1 EMIF_PHYCFG 0x0000010B local odt = 1, read latency = 11
+ */
+#define EMIF_PHYCFG (pg_val_ti816x(0x0000030B, 0x0000010B))
+
+#endif /* CONFIG_TI816X_EVM_DDR2 */
+#endif /* _DDR_DEFS_TI816X_H */
--
1.7.10.4
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