[U-Boot] [PATCH v2 06/16] sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i

[Siarhei Siamashka]

The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka at gmail.com>
---
Changes for v2:
   - this is a new patch in the series
   - reduce differences between sun4i/sun5i/sun7i to avoid conflicts
     when applying the follow-up patches

 arch/arm/cpu/armv7/sunxi/dram.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 33e8bd6..9042e9a 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -446,10 +446,6 @@ unsigned long dramc_init(struct dram_para *para)
 	/* Disable any pad power save control */
 	mctl_disable_power_save();
 
-	/* reset external DRAM */
-#ifndef CONFIG_SUN7I
-	mctl_ddr3_reset();
-#endif
 	mctl_set_drive();
 
 	/* dram clock off */
@@ -491,18 +487,11 @@ unsigned long dramc_init(struct dram_para *para)
 	reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
 	writel(reg_val, &dram->dcr);
 
-#ifdef CONFIG_SUN7I
 	dramc_clock_output_en(1);
-#endif
 
 	mctl_set_cke_delay();
 
-#ifdef CONFIG_SUN7I
 	mctl_ddr3_reset();
-#else
-	/* dram clock on */
-	dramc_clock_output_en(1);
-#endif
 
 	udelay(1);
 
-- 
1.8.3.2