[U-Boot] [PATCH v2 09/16] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)

[Ian Campbell]

On Sun, 2014-08-03 at 05:32 +0300, Siarhei Siamashka wrote:
> The sun5i hardware (Allwinner A13) introduced configurable MBUS clock
> speed. Allwinner A13 uses only 16-bit data bus width to connect the
> external DRAM, which is halved compared to the 32-bit data bus of sun4i
> (Allwinner A10), so it does not make much sense to clock a wider
> internal bus at a very high speed. The Allwinner A13 manual specifies
> 300 MHz MBUS clock speed limit and 533 MHz DRAM clock speed limit. Newer
> sun7i hardware (Allwinner A20) has a full width 32-bit external memory
> interface again, but still keeps the MBUS clock speed configurable.
> Clocking MBUS too low inhibits memory performance and one has to find
> the optimal MBUS/DRAM clock speed ratio, which may depend on many
> factors:
>     http://linux-sunxi.org/A10_DRAM_Controller_Performance
> 
> This patch introduces a new 'mbus_clock' parameter for the 'dram_para'
> struct and uses it as a desired MBUS clock speed target. If 'mbus_clock'
> is not set, 300 MHz is used by default to match the older hardcoded
> settings.
> 
> PLL5P and PLL6 are both evaluated as possible clock sources. Preferring
> the one, which can provide higher clock frequency that is lower or
> equal to the 'mbus_clock' target. In the case of a tie, PLL5P has
> higher priority.
> 
> Attempting to set the MBUS clock speed has no effect on sun4i, but does
> no harm either.
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka at gmail.com>

Acked-by: Ian Campbell <ijc at hellion.org.uk>