[U-Boot] [PATCH v2 13/16] sunxi: dram: Configurable DQS gating window mode and delay

[Ian Campbell]

On Sun, 2014-08-03 at 05:32 +0300, Siarhei Siamashka wrote:
> The hardware DQS gate training is a bit unreliable and does not
> always find the best delay settings.
> 
> So we introduce a 32-bit 'dqs_gating_delay' variable, where each
> byte encodes the DQS gating delay for each byte lane. The delay
> granularity is 1/4 cycle.
> 
> Also we allow to enable the active DQS gating window mode, which
> works better than the passive mode in practice. The DDR3 spec
> says that there is a 0.9 cycles preamble and 0.3 cycle postamble.
> The DQS window has to be opened during preamble and closed during
> postamble. In the passive window mode, the gating window is opened
> and closed by just using the gating delay settings. And because
> of the 1/4 cycle delay granularity, accurately hitting the 0.3
> cycle long postamble is a bit tough. In the active window mode,
> the gating window is auto-closing with the help of monitoring
> the DQS line, which relaxes the gating delay accuracy requirements.
> 
> But the hardware DQS gate training is still performed in the passive
> window mode. It is a more strict test, which is reducing the results
> variance compared to the training with active window mode.
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka at gmail.com>

Acked-by: Ian Campbell <ijc at hellion.org.uk>