[U-Boot] [PATCH] iMX6: Disable the L2 before chaning the PL310 latency

[Stefano Babic]

Hi Ye,

On 20/08/2014 11:18, Ye.Li wrote:
> From: "Ye.Li" <Ye.Li at freescale.com>
> 
> The Latency parameters of PL310 Tag RAM latency control register and
> Data RAM Latency control register are set in L2 cache enable. And
> setting these registers must have PL310 NOT enabled.
> 
> But when using Plugin mode boot, the PL310 is enabled by bootrom.
> The patch disables the PL310 before applying this setting.
> 
> Signed-off-by: Ye.Li <Ye.Li at freescale.com>
> ---
>  arch/arm/cpu/armv7/mx6/soc.c |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index f20bdeb..cc2231a 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -394,6 +394,9 @@ void v7_outer_cache_enable(void)
>  	}
>  #endif
>  
> +	/* Must disable the L2 before changing the latency parameters */
> +	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
> +
>  	writel(0x132, &pl310->pl310_tag_latency_ctrl);
>  	writel(0x132, &pl310->pl310_data_latency_ctrl);
> 


Acked-by: Stefano Babic <sbabic at denx.de>

Best regards,
Stefano Babic


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