[U-Boot] [PATCH V4 10/19] arm: mx6: ddr: configure MMDC for slow_pd

[Nikita Kiryanov]

According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).

Configure MMDC for slow pd.

Cc: Stefano Babic <sbabic at denx.de>
Cc: Tim Harvey <tharvey at gateworks.com>
Cc: Igor Grinberg <grinberg at compulab.co.il>
Acked-by: Igor Grinberg <grinberg at compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita at compulab.co.il>
---
Changes in V4:
	- No changes.

Changes in V3:
	- No changes.

Changes in V2:
	- Updated commit message to explain which bits in which registers
	  correspond to which settings.

 arch/arm/cpu/armv7/mx6/ddr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 70ce38f..c0fb749 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -463,6 +463,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mmdc0->mdpdc = (tcke & 0x7) << 16 |
 			5            << 12 |  /* PWDT_1: 256 cycles */
 			5            <<  8 |  /* PWDT_0: 256 cycles */
+			1            <<  7 |  /* SLOW_PD */
 			1            <<  6 |  /* BOTH_CS_PD */
 			(tcksrx & 0x7) << 3 |
 			(tcksre & 0x7);
-- 
1.9.1