[U-Boot] [PATCH v2 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Marek Vasut]

On Wednesday, August 20, 2014 at 11:24:35 PM, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
> 
> Adjust it accordingly.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
> Changes since v1:
> - Avoid too many ifdef's by providing a dma_rx_align() funtion as suggested
> by Otavio
> 
>  drivers/net/fec_mxc.c | 17 ++++++++++++++---
>  1 file changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 4cefda4..1a5105e 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -28,6 +28,8 @@ DECLARE_GLOBAL_DATA_PTR;
>   */
>  #define FEC_XFER_TIMEOUT	5000
> 
> +#define ARCH_DMA_MINALIGN_MX6SX	64
> +
>  #ifndef CONFIG_MII
>  #error "CONFIG_MII has to be defined!"
>  #endif
> @@ -267,6 +269,15 @@ static int fec_tx_task_disable(struct fec_priv *fec)
>  	return 0;
>  }
> 
> +static int dma_rx_align(void)
> +{
> +#ifdef CONFIG_MX6SX
> +	return	ARCH_DMA_MINALIGN_MX6SX;
> +#else
> +	return ARCH_DMA_MINALIGN;
> +#endif
> +}

This is not really an alignment, is it ? What is this really, cacheline length 
problem or what ? See RXDESC_PER_CACHELINE in the driver and make sure you don't 
break that mechanism as it would bite you ...

btw. you're using tab/space inconsistently past the 'return' keyword. Also, use 
the fec_ prefix in the functions in this driver consistently please.
[..]

Best regards,
Marek Vasut