[U-Boot] [PATCH] mx6: Fix cacheline size

[Benoît Thébaudeau]

Hi Fabio,

On Thu, Aug 21, 2014 at 9:11 PM, Fabio Estevam <festevam at gmail.com> wrote:
> On Thu, Aug 21, 2014 at 2:14 PM, Marek Vasut <marex at denx.de> wrote:
>> On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote:
>>> mx6 is an armv7 which has 64-byte cacheline size.
>>>
>>> Without this fix we are not able to get the FEC driver to work on mx6solox.
>>>
>>> 64-byte cacheline is also used by the kernel on ARMv7, so fix it
>>> accordingly.
>>
>> It's not a kernel thing, it's architecture thing. Otherwise,
>>
>> Acked-by: Marek Vasut <marex at denx.de>
>
> Actually the CortexA9 manual says:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Caccifbd.html
>
> "The cache line length is eight words."
>
> and the mx6q RM says:
>
> 12.5.4.1 L1 features
> ....
> • Eight 32-bit words per cache line
>
> So the current CONFIG_SYS_CACHELINE_SIZE of 32 is correct for mx6.

Yes, it's always 32 bytes for Cortex-A9. But does mx6solox really have
a standard Cortex-A9 core like all the currently released i.MX6 SoCs
(which seems to be the case according to
http://lwn.net/Articles/598434/), or a Cortex-A9 implementation with
non-standard parameters tuned by Freescale, or even another core like
a Cortex-A8?

> In kernel we use 64-bytes of cache line for armv7 though:
>
> config ARM_L1_CACHE_SHIFT_6
>     bool
>     default y if CPU_V7
>     help
>       Setting ARM L1 cache line size to 64 Bytes.

This seems to be used only for alignments, and stuff aligned with 64
bytes is also aligned with 32 bytes, so this should not matter.
However, [1] reads the cache line size from the registers, and it does
not use this constant.

Regards,
Benoît

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mm/cache-v7.S?id=refs/tags/v3.17-rc1