[U-Boot] [PATCH v2 2/3] pcie_imx: Add mx6solox support

[Fabio Estevam]

On Mon, Aug 25, 2014 at 4:54 AM, Marek Vasut <marex at denx.de> wrote:
> On Sunday, August 24, 2014 at 07:52:25 PM, Fabio Estevam wrote:
>
> [...]
>
>> --- a/arch/arm/cpu/armv7/mx6/clock.c
>> +++ b/arch/arm/cpu/armv7/mx6/clock.c
>> @@ -504,10 +504,19 @@ int enable_pcie_clock(void)
>>  #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN               (1 << 12)
>>  #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN               (1 << 10)
>>  #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK  0x0000001F
>> +#ifndef CONFIG_MX6SX
>> +     /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */
>>       clrsetbits_le32(&anatop_regs->ana_misc1,
>>                       ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
>>                       ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
>>                       ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
>> +#else
>> +     /* lvds_clk1 is sourced from pcie ref on imx6sx */
>> +     clrsetbits_le32(&anatop_regs->ana_misc1,
>> +                     ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
>> +                     ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
>> +                     ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa);
>> +#endif
>
> Is that only 1-bit difference here ? What does the magic 0xa and 0xb stand for
> please ?

Correct.

0xa means that LVDS1_CLK_SEL comes from PCIE_REF — PCIe ref clock

0xb means that LVDS1_CLK_SEL comes from SATA_REF — SATA ref clock

In this patch I have added comments for both cases, so hopefully it is clear.