[U-Boot] [PATCH v2 33/40] ARM: cache-cp15: Use more accurate types

[Simon Glass]

Hi Thierry,

On 26 August 2014 09:34, Thierry Reding <thierry.reding at gmail.com> wrote:
> From: Thierry Reding <treding at nvidia.com>
>
> size_t is the canonical type to represent variables that contain a size.
> Use it instead of signed integer. Physical addresses can be larger than
> 32-bit, so use a more appropriate type for them as well. phys_addr_t is
> a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
> the system is 64-bit or uses a form of physical address extension to use
> a larger address space on 32-bit systems. Using these types the same API
> can be implemented on a wider range of systems.
>
> Signed-off-by: Thierry Reding <treding at nvidia.com>
> ---
>  arch/arm/include/asm/system.h | 2 +-
>  arch/arm/lib/cache-cp15.c     | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
> index d51ba668f323..fb31a8faf2b1 100644
> --- a/arch/arm/include/asm/system.h
> +++ b/arch/arm/include/asm/system.h
> @@ -200,7 +200,7 @@ enum {
>   * \param size         size of memory region to change
>   * \param option       dcache option to select
>   */
> -void mmu_set_region_dcache_behaviour(u32 start, int size,
> +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
>                                      enum dcache_option option);
>
>  /**
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index 5fdfdbfca541..e6c1c83e5758 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -47,15 +47,15 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
>         debug("%s: Warning: not implemented\n", __func__);
>  }
>
> -void mmu_set_region_dcache_behaviour(u32 start, int size,
> +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
>                                      enum dcache_option option)
>  {
>         u32 *page_table = (u32 *)gd->arch.tlb_addr;
> -       u32 upto, end;
> +       unsigned long upto, end;
>
>         end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
>         start = start >> MMU_SECTION_SHIFT;
> -       debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
> +       debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,

The &start seems counter-intuitive. Can it not just be 'start'?

>               option);
>         for (upto = start; upto < end; upto++)
>                 set_section_dcache(upto, option);
> --
> 2.0.4
>

Regards,
Simon