[U-Boot] [PATCH v2 2/3] stv0991 : enable ethernet support.
Vikas Manocha
vikas.manocha at st.com
Fri Aug 29 14:08:41 CEST 2014
Signed-off-by: Vikas Manocha <vikas.manocha at st.com>
---
Changes in v2: None
arch/arm/cpu/armv7/stv0991/clock.c | 14 ++++++++
arch/arm/cpu/armv7/stv0991/pinmux.c | 14 ++++++++
arch/arm/include/asm/arch-stv0991/gpio.h | 22 ++++++++++++
arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 36 +++++++++++++++++++
arch/arm/include/asm/arch-stv0991/stv0991_creg.h | 13 +++++++
arch/arm/include/asm/arch-stv0991/stv0991_periph.h | 1 +
board/st/stv0991/stv0991.c | 37 ++++++++++++++++++++
include/configs/stv0991.h | 15 +++++++-
8 files changed, 151 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-stv0991/gpio.h
diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c
index aca6aba..70b8a8d 100644
--- a/arch/arm/cpu/armv7/stv0991/clock.c
+++ b/arch/arm/cpu/armv7/stv0991/clock.c
@@ -13,6 +13,13 @@
static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
+void enable_pll1(void)
+{
+ /* pll1 already configured for 1000Mhz, just need to enable it */
+ writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
+ &stv0991_cgu_regs->pll1_ctrl);
+}
+
void clock_setup(int peripheral)
{
switch (peripheral) {
@@ -20,6 +27,13 @@ void clock_setup(int peripheral)
writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
break;
case ETH_CLOCK_CFG:
+ enable_pll1();
+ writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
+
+ /* Clock selection for ethernet tx_clk & rx_clk*/
+ writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
+ | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
+
break;
default:
break;
diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c
index 6d4414a..1d086a2 100644
--- a/arch/arm/cpu/armv7/stv0991/pinmux.c
+++ b/arch/arm/cpu/armv7/stv0991/pinmux.c
@@ -41,6 +41,20 @@ int stv0991_pinmux_config(int peripheral)
CFG_GPIOB_16_UART_TX,
&stv0991_creg->mux7);
break;
+ case ETH_GPIOB_10_31_C_0_4:
+ writel(readl(&stv0991_creg->mux6) & 0x000000FF,
+ &stv0991_creg->mux6);
+ writel(0x00000000, &stv0991_creg->mux7);
+ writel(0x00000000, &stv0991_creg->mux8);
+ writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
+ &stv0991_creg->mux9);
+ /* Ethernet Voltage configuration to 1.8V*/
+ writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
+ ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
+ writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
+ ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
+
+ break;
default:
break;
}
diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h
new file mode 100644
index 0000000..9131ded
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/gpio.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha at st.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_STV0991_GPIO_H
+#define __ASM_ARCH_STV0991_GPIO_H
+
+enum gpio_direction {
+ GPIO_DIRECTION_IN,
+ GPIO_DIRECTION_OUT,
+};
+
+struct gpio_regs {
+ u32 data; /* offset 0x0 */
+ u32 reserved[0xff]; /* 0x4--0x3fc */
+ u32 dir; /* offset 0x400 */
+};
+
+#endif /* __ASM_ARCH_STV0991_GPIO_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
index 4926395..ddcbb57 100644
--- a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
@@ -77,4 +77,40 @@ struct stv0991_cgu_regs {
#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
| 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
+/* CGU Ethernet clock config */
+#define CLK_ETH_MCLK 0
+#define CLK_ETH_PLL1 1
+#define CLK_ETH_PLL2 2
+
+#define MDIV_SHIFT_ETH 3
+#define DIV_SHIFT_ETH 6
+#define DIV_ETH_125 9
+#define DIV_ETH_50 12
+#define DIV_ETH_P2P 15
+
+#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
+ | 1 << DIV_ETH_125 \
+ | 0 << DIV_SHIFT_ETH \
+ | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
+ /* CGU Ethernet control */
+
+#define ETH_CLK_TX_EXT_PHY 0
+#define ETH_CLK_TX_125M 1
+#define ETH_CLK_TX_25M 2
+#define ETH_CLK_TX_2M5 3
+#define ETH_CLK_TX_DIS 7
+
+#define ETH_CLK_RX_EXT_PHY 0
+#define ETH_CLK_RX_25M 1
+#define ETH_CLK_RX_2M5 2
+#define ETH_CLK_RX_DIS 3
+#define RX_CLK_SHIFT 3
+#define ETH_CLK_MASK ~(0x1F)
+
+#define ETH_PHY_MODE_GMII 0
+#define ETH_PHY_MODE_RMII 1
+#define ETH_PHY_CLK_DIS 1
+
+#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
+ | ETH_CLK_TX_EXT_PHY)
#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
index 045dbfe..c804eb5 100644
--- a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
@@ -79,4 +79,17 @@ struct stv0991_creg {
#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
+/* CREG Ethernet pad config */
+
+#define VDD_ETH_PS_1V8 0
+#define VDD_ETH_PS_2V5 2
+#define VDD_ETH_PS_3V3 3
+#define VDD_ETH_PS_MASK 0x3
+
+#define VDD_ETH_PS_SHIFT 12
+#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
+
+#define VDD_ETH_M_PS_SHIFT 28
+#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
+
#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
index f723771..f728c83 100644
--- a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
@@ -17,6 +17,7 @@
enum periph_id {
UART_GPIOC_30_31 = 0,
UART_GPIOB_16_17,
+ ETH_GPIOB_10_31_C_0_4,
PERIPH_ID_I2C0,
PERIPH_ID_I2C1,
PERIPH_ID_I2C2,
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
index bdeb53c..989fb5e 100644
--- a/board/st/stv0991/stv0991.c
+++ b/board/st/stv0991/stv0991.c
@@ -9,9 +9,16 @@
#include <miiphy.h>
#include <asm/arch/stv0991_periph.h>
#include <asm/arch/stv0991_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
+struct gpio_regs *const gpioa_regs =
+ (struct gpio_regs *) GPIOA_BASE_ADDR;
+
#ifdef CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress(int progress)
{
@@ -19,11 +26,26 @@ void show_boot_progress(int progress)
}
#endif
+void enable_eth_phy(void)
+{
+ /* Set GPIOA_06 pad HIGH (Appli board)*/
+ writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
+ writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
+}
+int board_eth_enable(void)
+{
+ stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
+ clock_setup(ETH_CLOCK_CFG);
+ enable_eth_phy();
+ return 0;
+}
+
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
+ board_eth_enable();
return 0;
}
@@ -33,6 +55,7 @@ int board_uart_init(void)
clock_setup(UART_CLOCK_CFG);
return 0;
}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
@@ -52,3 +75,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 37cfa7a..a7181b1 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -7,11 +7,11 @@
#ifndef __CONFIG_STV0991_H
#define __CONFIG_STV0991_H
-
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_BOARD_EARLY_INIT_F
+
#define CONFIG_SYS_CORTEX_R4
#define CONFIG_SYS_GENERIC_BOARD
@@ -55,4 +55,17 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+/* GMAC related configs */
+
+#define CONFIG_MII
+#define CONFIG_PHYLIB
+#define CONFIG_CMD_NET
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_PHY_MICREL
+
+/* Command support defines */
+#define CONFIG_CMD_PING
+#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+
#endif /* __CONFIG_H */
--
1.7.9.5
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