[U-Boot] [PATCH 1/2 v2] Exynos5800: The Peach-Pi board does not have a Parade video bridge

Simon Glass sjg at chromium.org
Mon Dec 1 21:30:08 CET 2014


Hi Sjoerd,

On 1 December 2014 at 13:25, Sjoerd Simons
<sjoerd.simons at collabora.co.uk> wrote:
> On Mon, 2014-12-01 at 13:09 -0700, Simon Glass wrote:
>> +Akshay
>>
>> Hi Sjoerd,
>>
>> On 1 December 2014 at 03:03, Sjoerd Simons
>> <sjoerd.simons at collabora.co.uk> wrote:
>> > Hey Simon,
>> >
>> > On Sun, 2014-11-30 at 11:56 -0700, Simon Glass wrote:
>> >> On 27 November 2014 at 08:08, Sjoerd Simons
>> >> <sjoerd.simons at collabora.co.uk> wrote:
>> >> > Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the
>> >> > Pi. So drop it from  device-tree
>> >> >
>> >> > Signed-off-by: Sjoerd Simons <sjoerd.simons at collabora.co.uk>
>> >> > ---
>> >> >  Changes since v1: Only modify the DTB
>> >> >
>> >> >  arch/arm/dts/exynos5800-peach-pi.dts | 5 -----
>> >> >  1 file changed, 5 deletions(-)
>> >>
>> >> Acked-by: Simon Glass <sjg at chromium.org>
>> >>
>> >> Tested on snow, pit, pi (display does not yet work on Pi).
>> >
>> > Just to be clear, in your testing does the display not work on Pi? It
>> > seems to be ok here (with u-boot starting chainloaded from one of the
>> > KERN partitions)
>>
>> That's right, not in U-Boot. I think this is because some GPIOs need
>> to be enabled to turn on the backlight etc. Maybe you have an EC which
>> turns these on automatically?
>>
>> If current mainline is supposed to make the display work on Pi then I
>> need to do some debugging. Please let me know.
>
> It does work on my machine, so i was wondering if it's a setup
> difference. I'm using the chained u-boot method (iotw the standard
> chromeos u-boot in flash starts main-line u-boot from mmc/SD), which
> might well mean that the GPIOs you're referring to are still turned on
> by the first u-boot (which it has to do to show me the unverified boot
> warning screen)?

Yes that's right. Maybe Akshay / Ajay have ideas, or otherwise I can
add this. I think it is two GPIOs, but it might be TPSCHROME also.

Regards,
Simon


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