[U-Boot] RFC Pin Configuration Device Tree Bindings for Altera Arria10 SOCFPGA

[Dinh Nguyen]

+CC: Matthew Gerlach

Not sure why the original submitter was left on this response.

On 12/3/14, 11:36 AM, Simon Glass wrote:
> Hi,
> 
> On 3 December 2014 at 06:48, Pavel Machek <pavel at ucw.cz> wrote:
>> Hi!
>>
>>> Altera Arria10 SOCFPGA Pin Configuration Bindings
>>>
>>> This document describes device tree bindings required to perform configuration
>>> of the pins for an Altera Arria10 SOCFPGA .  The bindings are intended to
>>> be compact and easy to be consumed only by a SPL running in a small on-chip
>>> ram before external memory is available.  The Arria10 SOCFPGA does not support
>>> dynamic modification of the pin configuration.
>>>
>>> Each set of pins is represented by its own subnode. For each subnode, the
>>> altr,pinmux-regs data will be written to sequential 32 bit addresses starting
>>> at the address in the reg property.
>>
>> These bindings will be incompatible with pin muxing on rest of
>> systems, right?
>>
>> Do we really want to parse DT in SPL? Should we parse the DT during
>> build for the SPL?
>>
>>                                                                 Pavel
>>
>>>
>>> Required properties:
>>>  - compatible : Must be "altr,arria10-pinmux" for Arria10 SOCFPGA
>>>  - one subnode for each set of pins to be configured
>>>
>>> Required subnode properties:
>>>  - reg : The start address to write pinmux-data as 32 bit quantities and the
>>>     number of bytes of registers to be written.
>>>  - altr,pinmux-regs : Pin configuration data to be written to registers
>>>
>>> Example:
>>>
>>> pinmux at 0xffd07000 {
>>>     #address-cells = <1>;
>>>     #size-cells = <0>;
>>>     compatible = "altr,arria10-pinmux";
>>>     shared {
>>>         reg = <0xffd07000 0x000000c0>;
>>>         altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF
>>>                    0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF
>>>                    0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xD 0xF 0xF
>>>                    0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF
>>>                    0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF>;
>>>     };
>>>     dedicated {
>>>         reg = <0xffd07200 0x00000044>;
>>>         altr,pinmux-regs = <0x0 0x0 0x0 0x8 0x8 0x8 0x8 0x8 0x8 0x8
>>>                    0xF 0xF 0xF 0xF 0xF 0xD 0xD>;
>>>     };
>>>     dedicated_cfg {
>>>         reg = <0xffd07300 0x00000048>;
>>>         altr,pinmux-regs = <0x00000 0x51010 0x51010 0x51010 0x40605
>>>                    0x40605 0x00605 0x40605 0x40605 0x40605
>>>                    0x10605 0x51010 0x51010 0x51010 0x51010
>>>                    0x51010 0x03030 0x23030>;
>>>     };
>>>     fpga {
>>>         reg = <0xffd07400 0x00000044>;
>>>         altr,pinmux-regs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
>>>                    0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
>>>     };
>>> };
> 
> Does this match the kernel? Or does the kernel have no such binding yet?
> 
> We can support this in SPL if required.
> 
> Regards,
> Simon
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