[U-Boot] [PATCH 05/25] x86: ich6-gpio: Make setup_pch_gpios() a weak function
Bin Meng
bmeng.cn at gmail.com
Thu Dec 4 16:00:58 CET 2014
Define a weak verion of setup_pch_gpios() in the ich6-gpio driver and
move the actual setup codes into the board support codes, so that the
driver does not need to know any platform specific stuff (ie: include
the platform specifc chipset header file).
Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
---
arch/x86/include/asm/arch-coreboot/gpio.h | 3 ++
arch/x86/include/asm/arch-ivybridge/gpio.h | 3 ++
board/google/chromebook_link/link.c | 40 +++++++++++++++++++++++
drivers/gpio/intel_ich6_gpio.c | 52 +++---------------------------
4 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h
index 4951a8c..31edef9 100644
--- a/arch/x86/include/asm/arch-coreboot/gpio.h
+++ b/arch/x86/include/asm/arch-coreboot/gpio.h
@@ -7,4 +7,7 @@
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x48
+
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h
index 4951a8c..31edef9 100644
--- a/arch/x86/include/asm/arch-ivybridge/gpio.h
+++ b/arch/x86/include/asm/arch-ivybridge/gpio.h
@@ -7,4 +7,7 @@
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x48
+
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 1822237..4d95c1c 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -7,6 +7,9 @@
#include <common.h>
#include <cros_ec.h>
#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
int arch_early_init_r(void)
{
@@ -121,3 +124,40 @@ int board_early_init_f(void)
return 0;
}
+
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+{
+ /* GPIO Set 1 */
+ if (gpio->set1.level)
+ outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
+ if (gpio->set1.mode)
+ outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+ if (gpio->set1.direction)
+ outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
+ if (gpio->set1.reset)
+ outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+ if (gpio->set1.invert)
+ outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
+ if (gpio->set1.blink)
+ outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+ /* GPIO Set 2 */
+ if (gpio->set2.level)
+ outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
+ if (gpio->set2.mode)
+ outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+ if (gpio->set2.direction)
+ outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+ if (gpio->set2.reset)
+ outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+ /* GPIO Set 3 */
+ if (gpio->set3.level)
+ outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
+ if (gpio->set3.mode)
+ outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+ if (gpio->set3.direction)
+ outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+ if (gpio->set3.reset)
+ outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b095d17..3a2e1b0 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -34,16 +34,9 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/pci.h>
-#ifdef CONFIG_X86_RESET_VECTOR
-#include <asm/arch/pch.h>
-#define SUPPORT_GPIO_SETUP
-#endif
#define GPIO_PER_BANK 32
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
struct ich6_bank_priv {
/* These are I/O addresses */
uint32_t use_sel;
@@ -51,44 +44,9 @@ struct ich6_bank_priv {
uint32_t lvl;
};
-#ifdef SUPPORT_GPIO_SETUP
-static void setup_pch_gpios(const struct pch_gpio_map *gpio)
+__weak void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
{
- u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
-
- /* GPIO Set 1 */
- if (gpio->set1.level)
- outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
- if (gpio->set1.mode)
- outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
- if (gpio->set1.direction)
- outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
- if (gpio->set1.reset)
- outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
- if (gpio->set1.invert)
- outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
- if (gpio->set1.blink)
- outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
-
- /* GPIO Set 2 */
- if (gpio->set2.level)
- outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
- if (gpio->set2.mode)
- outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
- if (gpio->set2.direction)
- outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
- if (gpio->set2.reset)
- outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
-
- /* GPIO Set 3 */
- if (gpio->set3.level)
- outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
- if (gpio->set3.mode)
- outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
- if (gpio->set3.direction)
- outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
- if (gpio->set3.reset)
- outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+ return;
}
/* TODO: Move this to device tree, or platform data */
@@ -96,7 +54,6 @@ void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd->arch.gpio_map = map;
}
-#endif /* SUPPORT_GPIO_SETUP */
static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
{
@@ -198,12 +155,11 @@ static int ich6_gpio_probe(struct udevice *dev)
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
struct ich6_bank_priv *bank = dev_get_priv(dev);
-#ifdef SUPPORT_GPIO_SETUP
if (gd->arch.gpio_map) {
- setup_pch_gpios(gd->arch.gpio_map);
+ setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
gd->arch.gpio_map = NULL;
}
-#endif
+
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
bank->use_sel = plat->base_addr;
--
1.8.2.1
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