[U-Boot] [PATCH v2 17/27] x86: ich6-gpio: Add Intel Tunnel Creek GPIO support

[Simon Glass]

On 9 December 2014 at 07:50, Bin Meng <bmeng.cn at gmail.com> wrote:
> Intel Tunnel Creek GPIO register block is compatible with current
> ich6-gpio driver, except the offset and content of GPIO block base
> address register in the LPC PCI configuration space are different.
>
> Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
> registers so that it could support both Ivybridge and Tunnel Creek.
>
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>

Acked-by: Simon Glass <sjg at chromium.org>

>
> ---
>
> Changes in v2:
> - Add a comment to explain we don't need check bit0 in GPIO base
>   address register
> - Add setup_pch_gpios() in crownbay.c
>
>  arch/x86/include/asm/arch-queensbay/gpio.h | 13 +++++++++++++
>  arch/x86/include/asm/gpio.h                |  4 ++--
>  board/coreboot/coreboot/coreboot.c         |  2 +-
>  board/google/chromebook_link/link.c        |  2 +-
>  board/intel/crownbay/crownbay.c            |  5 +++++
>  drivers/gpio/intel_ich6_gpio.c             | 20 ++++++++++++--------
>  6 files changed, 34 insertions(+), 12 deletions(-)
>  create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h
>
> diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h
> new file mode 100644
> index 0000000..ab4e059
> --- /dev/null
> +++ b/arch/x86/include/asm/arch-queensbay/gpio.h
> @@ -0,0 +1,13 @@
> +/*
> + * Copyright (C) 2014, Bin Meng <bmeng.cn at gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#ifndef _X86_ARCH_GPIO_H_
> +#define _X86_ARCH_GPIO_H_
> +
> +/* Where in config space is the register that points to the GPIO registers? */
> +#define PCI_CFG_GPIOBASE 0x44
> +
> +#endif /* _X86_ARCH_GPIO_H_ */
> diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
> index 1787e52..1099427 100644
> --- a/arch/x86/include/asm/gpio.h
> +++ b/arch/x86/include/asm/gpio.h
> @@ -11,7 +11,7 @@
>  #include <asm-generic/gpio.h>
>
>  struct ich6_bank_platdata {
> -       uint32_t base_addr;
> +       uint16_t base_addr;
>         const char *bank_name;
>  };
>
> @@ -147,7 +147,7 @@ struct pch_gpio_map {
>         } set3;
>  };
>
> -void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio);
> +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
>  void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
>
>  #endif /* _X86_GPIO_H_ */
> diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
> index b260f9a..154faf6 100644
> --- a/board/coreboot/coreboot/coreboot.c
> +++ b/board/coreboot/coreboot/coreboot.c
> @@ -16,7 +16,7 @@ int arch_early_init_r(void)
>         return 0;
>  }
>
> -void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
> +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
>  {
>         return;
>  }
> diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
> index 4d95c1c..9978e92 100644
> --- a/board/google/chromebook_link/link.c
> +++ b/board/google/chromebook_link/link.c
> @@ -125,7 +125,7 @@ int board_early_init_f(void)
>         return 0;
>  }
>
> -void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
> +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
>  {
>         /* GPIO Set 1 */
>         if (gpio->set1.level)
> diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
> index 8c6df98..54670d3 100644
> --- a/board/intel/crownbay/crownbay.c
> +++ b/board/intel/crownbay/crownbay.c
> @@ -19,3 +19,8 @@ int board_early_init_f(void)
>
>         return 0;
>  }
> +
> +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
> +{
> +       return;
> +}
> diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
> index 1f0d9df..5f67b3f 100644
> --- a/drivers/gpio/intel_ich6_gpio.c
> +++ b/drivers/gpio/intel_ich6_gpio.c
> @@ -39,9 +39,9 @@
>
>  struct ich6_bank_priv {
>         /* These are I/O addresses */
> -       uint32_t use_sel;
> -       uint32_t io_sel;
> -       uint32_t lvl;
> +       uint16_t use_sel;
> +       uint16_t io_sel;
> +       uint16_t lvl;
>  };
>
>  /* TODO: Move this to device tree, or platform data */
> @@ -57,7 +57,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
>         u8 tmpbyte;
>         u16 tmpword;
>         u32 tmplong;
> -       u32 gpiobase;
> +       u16 gpiobase;
>         int offset;
>
>         /* Where should it be? */
> @@ -116,11 +116,15 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
>         /*
>          * GPIOBASE moved to its current offset with ICH6, but prior to
>          * that it was unused (or undocumented). Check that it looks
> -        * okay: not all ones or zeros, and mapped to I/O space (bit 0).
> +        * okay: not all ones or zeros.
> +        *
> +        * Note we don't need check bit0 here, because the Tunnel Creek
> +        * GPIO base address register bit0 is reserved (read returns 0),
> +        * while on the Ivybridge the bit0 is used to indicate it is an
> +        * I/O space.
>          */
>         tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
> -       if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
> -           !(tmplong & 0x00000001)) {
> +       if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
>                 debug("%s: unexpected GPIOBASE value\n", __func__);
>                 return -ENODEV;
>         }
> @@ -131,7 +135,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
>          * at the offset that we just read. Bit 0 indicates that it's
>          * an I/O address, not a memory address, so mask that off.
>          */
> -       gpiobase = tmplong & 0xfffffffe;
> +       gpiobase = tmplong & 0xfffe;
>         offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
>         if (offset == -1) {
>                 debug("%s: Invalid register offset %d\n", __func__, offset);
> --
> 1.8.2.1
>