[U-Boot] [PATCH v2 19/27] x86: Add queensbay and crownbay Kconfig files

[Simon Glass]

On 9 December 2014 at 07:50, Bin Meng <bmeng.cn at gmail.com> wrote:
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
>
> ---
>
> Changes in v2:
> - Fix several typos in queensbay/Kconfig
> - Change FSP_FILE and CMC_FILE description to indicate the file is
>   in the board directory
> - Add help for FSP_TEMP_RAM_ADDR
> - Add more help for CMC_FILE

Acked-by: Simon Glass <sjg at chromium.org>

>
>  arch/x86/Kconfig               | 13 +++++++
>  arch/x86/cpu/queensbay/Kconfig | 79 ++++++++++++++++++++++++++++++++++++++++++
>  board/intel/crownbay/Kconfig   | 20 +++++++++++
>  3 files changed, 112 insertions(+)
>  create mode 100644 arch/x86/cpu/queensbay/Kconfig
>  create mode 100644 board/intel/crownbay/Kconfig
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index fdfb618..ebf72b3 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK
>           and it provides a 2560x1700 high resolution touch-enabled LCD
>           display.
>
> +config TARGET_CROWNBAY
> +       bool "Support Intel Crown Bay CRB"
> +       help
> +         This is the Intel Crown Bay Customer Reference Board. It contains
> +         the Intel Atom Processor E6xx populated on the COM Express module
> +         with 1GB DDR2 soldered down memory and a carrier board with the
> +         Intel Platform Controller Hub EG20T, other system components and
> +         peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
> +
>  endchoice
>
>  config RAMBASE
> @@ -310,8 +319,12 @@ endmenu
>
>  source "arch/x86/cpu/ivybridge/Kconfig"
>
> +source "arch/x86/cpu/queensbay/Kconfig"
> +
>  source "board/coreboot/coreboot/Kconfig"
>
>  source "board/google/chromebook_link/Kconfig"
>
> +source "board/intel/crownbay/Kconfig"
> +
>  endmenu
> diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
> new file mode 100644
> index 0000000..56fe85c
> --- /dev/null
> +++ b/arch/x86/cpu/queensbay/Kconfig
> @@ -0,0 +1,79 @@
> +#
> +# Copyright (C) 2014, Bin Meng <bmeng.cn at gmail.com>
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +config INTEL_QUEENSBAY
> +       bool
> +       select HAVE_FSP
> +       select HAVE_CMC
> +
> +if INTEL_QUEENSBAY
> +
> +config HAVE_FSP
> +       bool "Add an Firmware Support Package binary"
> +       help
> +         Select this option to add an Firmware Support Package binary to
> +         the resulting U-Boot image. It is a binary blob which U-Boot uses
> +         to set up SDRAM and other chipset specific initialization.
> +
> +         Note: Without this binary U-Boot will not be able to set up its
> +         SDRAM so will not boot.
> +
> +config FSP_FILE
> +       string "Firmware Support Package binary filename"
> +       depends on HAVE_FSP
> +       default "fsp.bin"
> +       help
> +         The filename of the file to use as Firmware Support Package binary
> +         in the board directory.
> +
> +config FSP_LOCATION
> +       hex "Firmware Support Package binary location"
> +       depends on HAVE_FSP
> +       default 0xfffc0000
> +       help
> +         FSP is not Position Independent Code (PIC) and the whole FSP has to
> +         be rebased if it is placed at a location which is different from the
> +         perferred base address specified during the FSP build. Use Intel's
> +         Binary Configuration Tool (BCT) to do the rebase.
> +
> +         The default base address of 0xfffc0000 indicates that the binary must
> +         be located at offset 0xc0000 from the beginning of a 1MB flash device.
> +
> +config FSP_TEMP_RAM_ADDR
> +       hex
> +       default 0x2000000
> +       help
> +         Stack top address which is used in FspInit after DRAM is ready and
> +         CAR is disabled.
> +
> +config HAVE_CMC
> +       bool "Add a Chipset Micro Code state machine binary"
> +       help
> +         Select this option to add a Chipset Micro Code state machine binary
> +         to the resulting U-Boot image. It is a 64K data block of machine
> +         specific code which must be put in the flash for the processor to
> +         access when powered up before system BIOS is executed.
> +
> +config CMC_FILE
> +       string "Chipset Micro Code state machine filename"
> +       depends on HAVE_CMC
> +       default "cmc.bin"
> +       help
> +         The filename of the file to use as Chipset Micro Code state machine
> +         binary in the board directory.
> +
> +config CMC_LOCATION
> +       hex "Chipset Micro Code state machine binary location"
> +       depends on HAVE_CMC
> +       default 0xfffb0000
> +       help
> +         The location of the CMC binary is determined by a strap. It must be
> +         put in flash at a location matching the strap-determined base address.
> +
> +         The default base address of 0xfffb0000 indicates that the binary must
> +         be located at offset 0xb0000 from the beginning of a 1MB flash device.
> +
> +endif
> diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
> new file mode 100644
> index 0000000..4709f9b
> --- /dev/null
> +++ b/board/intel/crownbay/Kconfig
> @@ -0,0 +1,20 @@
> +if TARGET_CROWNBAY
> +
> +config SYS_BOARD
> +       default "crownbay"
> +
> +config SYS_VENDOR
> +       default "intel"
> +
> +config SYS_SOC
> +       default "queensbay"
> +
> +config SYS_CONFIG_NAME
> +       default "crownbay"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +       def_bool y
> +       select INTEL_QUEENSBAY
> +       select BOARD_ROMSIZE_KB_1024
> +
> +endif
> --
> 1.8.2.1
>