[U-Boot] [PATCH v3 0/27] x86: Add Intel Queensbay platform support
Bin Meng
bmeng.cn at gmail.com
Fri Dec 12 14:05:18 CET 2014
This patch series add the Intel Queensbay platform support. The Queensbay
platform includes an Atom E6xx processor (codename Tunnel Creek) and a
Platform Controller Hub EG20T (codename Topcliff). The support depends
on Intel Firmware Support Package (FSP) to initialize the processor and
chipset including system memory. With this patch series, U-Boot boots to
Linux kernel. Validated on an Intel Crown Bay board with kernel 3.17.
Changes in v3:
- Apply U-Boot coding conventions to typedefs in FSP codes
- Use jnz to jump to the car_init error code at the end of tnc_car.S
file instead of being in the normal path flow
- Add a TODO comment block to document the fsp_init() call
- Change label xxx_stack to xxx_romstack in tnc_car.S
- Add a comment block to explain the ROM stack
- Add a commit message for the SPI support
Changes in v2:
- tools/ifdtool: Change WRITE_NUM to WRITE_MAX
- tools/ifdtool: Remove the unnecessary initialiser of addr and wr_fname
- Move setup_pch_gpios() to board support codes instead of
making it a weak function
- Add a comment to describe PNP_DEV
- Change pnp device inline routine parameters to use proper size
- Apply U-Boot coding convention to the FSP support codes
- Update the codes to use U-Boot coding style
- Move FspInit call from start.S to car_init
- Use ARRAY_SIZE to indicate the maximum number of HOB tyeps
- Remove some unnecessary spaces in the do_hob command output
- Replace 0xcf9 with macro PORT_RESET from processor.h
- Move FspInit call from start.S to car_init
- Add UART0_BASE and UART1_BASE to ibmpc.h
- Add a comment to explain we don't need check bit0 in GPIO base
address register
- Add setup_pch_gpios() in crownbay.c
- Fix several typos in queensbay/Kconfig
- Change FSP_FILE and CMC_FILE description to indicate the file is
in the board directory
- Add help for FSP_TEMP_RAM_ADDR
- Add more help for CMC_FILE
- New patch to use consistent name XXX_ADDR for binary blobs
- Update ifdtool flags to indicate FSP and CMC files are in
the board directory
- Use consistent XXX_FILE name for binary blob file
- Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h
- Check return value of x86_cpu_init_f()
- Use ARRAY_SIZE(mmc_supported) instead of 2
- Check return value of add_sdhci()
- New patch to rename coreboot-serial to x86-serial
- Remove the 'make menuconfig' in the crownbay build instructions
- Indicate all the binary blobs should be put in the board directory
Bin Meng (27):
x86: Make ROM_SIZE configurable in Kconfig
tools/ifdtool: Support writing multiple files (-w) simultaneously
x86: Refactor u-boot.rom build rules
x86: Clean up asm-offsets
x86: ich6-gpio: Move setup_pch_gpios() to board support codes
x86: Add Intel Crown Bay board dts file
x86: Add a simple superio driver for SMSC LPC47M
x86: Add Intel Topcliff PCH device IDs
x86: ich-spi: Add Intel Tunnel Creek SPI controller support
x86: Initial import from Intel FSP release for Queensbay platform
x86: queensbay: Adapt FSP support codes
x86: Add post failure codes for bist and car
x86: Support Intel FSP initialization path in start.S
x86: Add a simple command to show FSP HOB information
x86: Integrate Tunnel Creek processor microcode
x86: Add basic support to queensbay platform and crownbay board
x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
x86: Enable the queensbay cpu directory build
x86: Add queensbay and crownbay Kconfig files
x86: Add crownbay defconfig and config.h
x86: Use consistent name XXX_ADDR for binary blob flash address
x86: Include FSP and CMC binary in the u-boot.rom build rules
x86: crownbay: Add SPI flash support
x86: crownbay: Enable Intel E1000 NIC support
x86: crownbay: Add SDHCI support
x86: Rename coreboot-serial to x86-serial
x86: Add a README.x86 for U-Boot on x86 support
Makefile | 56 +-
arch/x86/Kconfig | 91 +-
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c | 1 +
arch/x86/cpu/ivybridge/sdram.c | 2 +-
arch/x86/cpu/queensbay/Kconfig | 79 ++
arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++
arch/x86/cpu/queensbay/Makefile | 9 +
arch/x86/cpu/queensbay/fsp_configs.c | 20 +
arch/x86/cpu/queensbay/fsp_support.c | 416 +++++++
arch/x86/cpu/queensbay/tnc.c | 72 ++
arch/x86/cpu/queensbay/tnc_car.S | 127 ++
arch/x86/cpu/queensbay/tnc_dram.c | 78 ++
arch/x86/cpu/queensbay/tnc_pci.c | 61 +
arch/x86/cpu/queensbay/topcliff.c | 47 +
arch/x86/cpu/start.S | 17 +-
arch/x86/dts/Makefile | 3 +-
arch/x86/dts/coreboot.dtsi | 2 +-
arch/x86/dts/crownbay.dts | 53 +
arch/x86/include/asm/arch-coreboot/gpio.h | 3 +
arch/x86/include/asm/arch-ivybridge/gpio.h | 3 +
arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h | 59 +
.../include/asm/arch-queensbay/fsp/fsp_bootmode.h | 24 +
arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h | 158 +++
arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h | 137 +++
arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h | 310 +++++
.../asm/arch-queensbay/fsp/fsp_infoheader.h | 36 +
.../include/asm/arch-queensbay/fsp/fsp_platform.h | 19 +
.../include/asm/arch-queensbay/fsp/fsp_support.h | 198 +++
.../x86/include/asm/arch-queensbay/fsp/fsp_types.h | 97 ++
arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 58 +
arch/x86/include/asm/arch-queensbay/gpio.h | 13 +
arch/x86/include/asm/arch-queensbay/tnc.h | 15 +
arch/x86/include/asm/global_data.h | 3 +
arch/x86/include/asm/gpio.h | 3 +-
arch/x86/include/asm/ibmpc.h | 3 +
arch/x86/include/asm/pnp_def.h | 90 ++
arch/x86/include/asm/post.h | 2 +
arch/x86/lib/Makefile | 1 +
arch/x86/lib/asm-offsets.c | 5 +-
arch/x86/lib/cmd_hob.c | 67 +
board/coreboot/coreboot/coreboot.c | 6 +
board/google/chromebook_link/Kconfig | 1 +
board/google/chromebook_link/link.c | 40 +
board/intel/crownbay/Kconfig | 20 +
board/intel/crownbay/MAINTAINERS | 6 +
board/intel/crownbay/Makefile | 7 +
board/intel/crownbay/crownbay.c | 32 +
board/intel/crownbay/start.S | 9 +
configs/crownbay_defconfig | 6 +
doc/README.x86 | 126 ++
drivers/gpio/intel_ich6_gpio.c | 73 +-
drivers/misc/Makefile | 1 +
drivers/misc/smsc_lpc47m.c | 33 +
drivers/serial/Makefile | 2 +-
drivers/serial/{serial_coreboot.c => serial_x86.c} | 12 +-
drivers/spi/ich.c | 3 +-
include/configs/chromebook_link.h | 6 +-
include/configs/coreboot.h | 2 +-
include/configs/crownbay.h | 61 +
include/pci_ids.h | 8 +
include/smsc_lpc47m.h | 19 +
lib/asm-offsets.c | 3 -
tools/ifdtool.c | 31 +-
tools/ifdtool.h | 2 +
65 files changed, 4127 insertions(+), 109 deletions(-)
create mode 100644 arch/x86/cpu/queensbay/Kconfig
create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc
create mode 100644 arch/x86/cpu/queensbay/Makefile
create mode 100644 arch/x86/cpu/queensbay/fsp_configs.c
create mode 100644 arch/x86/cpu/queensbay/fsp_support.c
create mode 100644 arch/x86/cpu/queensbay/tnc.c
create mode 100644 arch/x86/cpu/queensbay/tnc_car.S
create mode 100644 arch/x86/cpu/queensbay/tnc_dram.c
create mode 100644 arch/x86/cpu/queensbay/tnc_pci.c
create mode 100644 arch/x86/cpu/queensbay/topcliff.c
create mode 100644 arch/x86/dts/crownbay.dts
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h
create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h
create mode 100644 arch/x86/include/asm/pnp_def.h
create mode 100644 arch/x86/lib/cmd_hob.c
create mode 100644 board/intel/crownbay/Kconfig
create mode 100644 board/intel/crownbay/MAINTAINERS
create mode 100644 board/intel/crownbay/Makefile
create mode 100644 board/intel/crownbay/crownbay.c
create mode 100644 board/intel/crownbay/start.S
create mode 100644 configs/crownbay_defconfig
create mode 100644 doc/README.x86
create mode 100644 drivers/misc/smsc_lpc47m.c
rename drivers/serial/{serial_coreboot.c => serial_x86.c} (67%)
create mode 100644 include/configs/crownbay.h
create mode 100644 include/smsc_lpc47m.h
--
1.8.2.1
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