[U-Boot] [PATCH 1/4] sunxi: video: Fix tcon0 hsync / vsync setting
Hans de Goede
hdegoede at redhat.com
Sat Dec 27 16:53:48 CET 2014
It turns out that the problems I was seeing were due to a bad powersupply,
so enable proper negative hsync / vsync support.
Also adjust various defconfigs to keep the hsync and vsync for the lcd
panels positive, changing sync:0 into sync:3.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
---
arch/arm/include/asm/arch-sunxi/display.h | 2 ++
configs/A10s-OLinuXino-M-lcd7_defconfig | 2 +-
configs/A13-OLinuXinoM_defconfig | 2 +-
configs/A13-OLinuXino_defconfig | 2 +-
configs/A20-OLinuXino_MICRO-lcd7_defconfig | 2 +-
configs/Ippo_q8h_v1_2_defconfig | 2 +-
configs/Ippo_q8h_v5_defconfig | 2 +-
drivers/video/sunxi_display.c | 15 ++++++++-------
8 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
index dcb2fe4..908c5d9 100644
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -174,6 +174,8 @@ struct sunxi_hdmi_reg {
*/
#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
+#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
+#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
diff --git a/configs/A10s-OLinuXino-M-lcd7_defconfig b/configs/A10s-OLinuXino-M-lcd7_defconfig
index eafa974..cbaa04d 100644
--- a/configs/A10s-OLinuXino-M-lcd7_defconfig
+++ b/configs/A10s-OLinuXino-M-lcd7_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
-CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PB9"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+S:CONFIG_MMC0_CD_PIN="PG1"
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 7790460..1a99418 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -6,7 +6,7 @@ CONFIG_VIDEO_HDMI=n
CONFIG_VIDEO_VGA_VIA_LCD=y
# For use with the Olimex 7" LCD module, adjust timings for other displays
# Set video-mode=sunxi:800x600-24 at 60,monitor=lcd in the env. to enable
-CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+S:CONFIG_ARM=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 944f2e5..7df6951 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -6,7 +6,7 @@ CONFIG_VIDEO_HDMI=n
CONFIG_VIDEO_VGA_VIA_LCD=y
# For use with the Olimex 7" LCD module, adjust timings for other displays
# Set video-mode=sunxi:800x600-24 at 60,monitor=lcd in the env. to enable
-CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+S:CONFIG_ARM=y
diff --git a/configs/A20-OLinuXino_MICRO-lcd7_defconfig b/configs/A20-OLinuXino_MICRO-lcd7_defconfig
index 05674d7..71afbff 100644
--- a/configs/A20-OLinuXino_MICRO-lcd7_defconfig
+++ b/configs/A20-OLinuXino_MICRO-lcd7_defconfig
@@ -2,7 +2,7 @@ CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+S:CONFIG_MMC0_CD_PIN="PH1"
diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig
index b1d07c5..0447b06 100644
--- a/configs/Ippo_q8h_v1_2_defconfig
+++ b/configs/Ippo_q8h_v1_2_defconfig
@@ -1,7 +1,7 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v1.2.dtb"
-CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:0,vmode:0"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
index f3dadca..4e82bf9 100644
--- a/configs/Ippo_q8h_v5_defconfig
+++ b/configs/Ippo_q8h_v5_defconfig
@@ -1,7 +1,7 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb"
-CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:0,vmode:0"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index a20ff57..669c46c 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -506,7 +506,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
- int bp, clk_delay, clk_div, clk_double, pin, total;
+ int bp, clk_delay, clk_div, clk_double, pin, total, val;
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
@@ -561,12 +561,13 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
&lcdc->frame_ctrl[0]);
}
- /*
- * Bit 24 and 25 of tcon0_io_polarity can be used to invert hsync /
- * vsync polarity, but this leads to noise problems, so we always
- * keep the polarity positive.
- */
- writel(0, &lcdc->tcon0_io_polarity);
+ val = 0;
+ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
+ val |= SUNXI_LCDC_TCON_HSYNC_MASK;
+ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
+ val |= SUNXI_LCDC_TCON_VSYNC_MASK;
+ writel(val, &lcdc->tcon0_io_polarity);
+
writel(0, &lcdc->tcon0_io_tristate);
}
--
2.1.0
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