[U-Boot] [PATCH 2/2] sunxi: clock_sun6i: Remove "magic" m and k params from clock_set_pll5

[Hans de Goede]

Let clock_set_pll5 pick the optimal m and k values itself based on the
requested rate, rather then passing them in as magic constants.

Suggested-by: Siarhei Siamashka <siarhei.siamashka at gmail.com>
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
---
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 9 ++++++++-
 arch/arm/cpu/armv7/sunxi/dram_sun6i.c         | 2 +-
 arch/arm/cpu/armv7/sunxi/dram_sun8i.c         | 2 +-
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 +-
 4 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 36e502f..d7a7040 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -148,15 +148,22 @@ void clock_set_pll3(unsigned int clk)
 	       &ccm->pll3_cfg);
 }
 
-void clock_set_pll5(unsigned int clk, int k, int m, bool sigma_delta_enable)
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 {
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	const int max_n = 32;
+	int k = 1, m = 2;
 
 	if (sigma_delta_enable)
 		writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
 
 	/* PLL5 rate = 24000000 * n * k / m */
+	if (clk > 24000000 * k * max_n / m) {
+		m = 1;
+		if (clk > 24000000 * k * max_n / m)
+			k = 2;
+	}
 	writel(CCM_PLL5_CTRL_EN |
 	       (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
 	       CCM_PLL5_CTRL_UPD |
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
index 4518b80..5dbbf61 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
@@ -33,7 +33,7 @@ static void mctl_sys_init(void)
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	const int dram_clk_div = 2;
 
-	clock_set_pll5(DRAM_CLK * dram_clk_div, 2, 1, false);
+	clock_set_pll5(DRAM_CLK * dram_clk_div, false);
 
 	clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
 		CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
index ebba53b..3d7964d 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
@@ -61,7 +61,7 @@ static void mctl_sys_init(void)
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
 	/* enable pll5, note the divide by 2 is deliberate! */
-	clock_set_pll5(dram_para.clock * 1000000 / 2, 1, 2,
+	clock_set_pll5(dram_para.clock * 1000000 / 2,
 		       dram_para.tpr13 & 0x40000);
 
 	/* deassert ahb mctl reset */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 0e57abe..653f63c 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -317,6 +317,6 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_PLL10		(5 << 24)
 #define CCM_DE_CTRL_GATE		(1 << 31)
 
-void clock_set_pll5(unsigned int clk, int k, int m, bool sigma_delta_enable);
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
 
 #endif /* _SUNXI_CLOCK_SUN6I_H */
-- 
2.1.0