[U-Boot] [PATCH v3 2/7] x86: Support pci bus scan in the early phase

[Bin Meng]

On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
Acked-by: Simon Glass <sjg at chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 404fbb6..1eee08b 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -29,6 +29,7 @@ int pci_early_init_hose(struct pci_controller **hosep)
 
 	board_pci_setup_hose(hose);
 	pci_setup_type1(hose);
+	hose->last_busno = pci_hose_scan(hose);
 	gd->arch.hose = hose;
 	*hosep = hose;
 
-- 
1.8.2.1