[U-Boot] [PATCH 1/4] kirkwood: Rename dns325 to dnskw
Bastien ROUCARIÈS
roucaries.bastien at gmail.com
Sun Jun 8 18:30:25 CEST 2014
From: Jamie Lentin <jm at lentin.co.uk>
So we can re-use DNS-325 configuration for the DNS-320 without things getting
confusing, rename all common parts from dns325 to dnskw, and use a config
option to configure DNS-325 specifics.
Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
Cc: prafulla at marvell.com
Cc: albert.u.boot at aribaud.net
---
board/d-link/dns325/Makefile | 13 ---
board/d-link/dns325/dns325.c | 132 -----------------------
board/d-link/dns325/dns325.h | 32 ------
board/d-link/dns325/kwbimage.cfg | 192 ---------------------------------
board/d-link/dnskw/Makefile | 13 +++
board/d-link/dnskw/dnskw.c | 132 +++++++++++++++++++++++
board/d-link/dnskw/dnskw.h | 36 +++++++
board/d-link/dnskw/kwbimage.dns325.cfg | 192 +++++++++++++++++++++++++++++++++
boards.cfg | 2 +-
include/configs/dns325.h | 170 -----------------------------
include/configs/dnskw.h | 175 ++++++++++++++++++++++++++++++
11 files changed, 549 insertions(+), 540 deletions(-)
delete mode 100644 board/d-link/dns325/Makefile
delete mode 100644 board/d-link/dns325/dns325.c
delete mode 100644 board/d-link/dns325/dns325.h
delete mode 100644 board/d-link/dns325/kwbimage.cfg
create mode 100644 board/d-link/dnskw/Makefile
create mode 100644 board/d-link/dnskw/dnskw.c
create mode 100644 board/d-link/dnskw/dnskw.h
create mode 100644 board/d-link/dnskw/kwbimage.dns325.cfg
delete mode 100644 include/configs/dns325.h
create mode 100644 include/configs/dnskw.h
diff --git a/board/d-link/dns325/Makefile b/board/d-link/dns325/Makefile
deleted file mode 100644
index b8a5ea1..0000000
--- a/board/d-link/dns325/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (C) 2011
-# Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dns325.o
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c
deleted file mode 100644
index ff70e94..0000000
--- a/board/d-link/dns325/dns325.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-#include "dns325.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* Gpio configuration */
- kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
- DNS325_OE_LOW, DNS325_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_SATA1_ACTn, /* sata1(left) status led */
- MPP21_SATA0_ACTn, /* sata0(right) status led */
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO, /* power off out */
- MPP25_GPIO,
- MPP26_GPIO, /* power led */
- MPP27_GPIO, /* sata0(right) error led */
- MPP28_GPIO, /* sata1(left) error led */
- MPP29_GPIO, /* usb error led */
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO, /* power key */
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO, /* enable sata 0 */
- MPP40_GPIO, /* enable sata 1 */
- MPP41_GPIO, /* hdd0 present */
- MPP42_GPIO, /* hdd1 present */
- MPP43_GPIO, /* usb status led */
- MPP44_GPIO, /* fan status */
- MPP45_GPIO, /* fan high speed */
- MPP46_GPIO, /* fan low speed */
- MPP47_GPIO, /* usb umount */
- MPP48_GPIO, /* factory reset */
- MPP49_GPIO, /* thermal sensor */
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
-
- kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
- return 0;
-}
-
-int board_init(void)
-{
- /* Boot parameters address */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..(%s) could not read PHY dev address\n", __func__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- debug("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dns325/dns325.h
deleted file mode 100644
index f7b25f2..0000000
--- a/board/d-link/dns325/dns325.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __DNS325_H
-#define __DNS325_H
-
-/* GPIO configuration */
-#define DNS325_OE_LOW 0x00000000
-#define DNS325_OE_HIGH 0x00039604
-#define DNS325_OE_VAL_LOW 0x38000000 /* disable leds */
-#define DNS325_OE_VAL_HIGH 0x00000800 /* disable leds */
-
-#define DNS325_GPIO_LED_POWER 26
-#define DNS325_GPIO_SATA0_EN 39
-#define DNS325_GPIO_SATA1_EN 40
-
-/* PHY related */
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __DNS325_H */
diff --git a/board/d-link/dns325/kwbimage.cfg b/board/d-link/dns325/kwbimage.cfg
deleted file mode 100644
index b69c1df..0000000
--- a/board/d-link/dns325/kwbimage.cfg
+++ /dev/null
@@ -1,192 +0,0 @@
-#
-# Copyright (C) 2011
-# Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30, 3120 DDR2 clks refresh rate
-# bit23-14: 0 required
-# bit24: 1, enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: 0 required
-# bit31-30: 0b01 required
-
-DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
-# bit3-0: 0 required
-# bit4: 0, addr/cmd in smame cycle
-# bit5: 0, clk is driven during self refresh, we don't care for APX
-# bit6: 0, use recommended falling edge of clk for addr/cmd
-# bit11-7: 0 required
-# bit12: 1 required
-# bit13: 1 required
-# bit14: 0, input buffer always powered up
-# bit17-15: 0 required
-# bit18: 1, cpu lock transaction enabled
-# bit19: 0 required
-# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0, no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
-# bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
-# bit7-4: 5, 6 cycle tRCD
-# bit11-8: 4, 5 cyle tRP
-# bit15-12: 5, 6 cyle tWR
-# bit19-16: 2, 3 cyle tWTR
-# bit20: 1, 18 cycle tRAS (tRAS[4])
-# bit23-21: 0 required
-# bit27-24: 2, 3 cycle tRRD
-# bit31-28: 2, 3 cyle tRTP
-
-DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
-# bit6-0: 0x33, 33 cycle tRFC
-# bit8-7: 0, 1 cycle tR2R
-# bit10-9: 0, 1 cyle tR2W
-# bit12-11: 1, 2 cylce tW2W
-# bit31-13: 0 required
-
-DATA 0xFFD01410 0x0000000c # DDR Address Control
-# bit1-0: 0, Cs0width=x8
-# bit3-2: 3, Cs0size=1Gb
-# bit5-4: 0, Cs1width=nonexistent
-# bit7-6: 0, Cs1size=nonexistent
-# bit9-8: 0, Cs2width=nonexistent
-# bit11-10: 0, Cs2size=nonexistent
-# bit13-12: 0, Cs3width=nonexistent
-# bit15-14: 0, Cs3size=nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OPEn=OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0, Cmd=Normal SDRAM Mode
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, Burst Length (2 required)
-# bit3: 0, Burst Type (0 required)
-# bit6-4: 5, CAS Latency (CL) 5
-# bit7: 0, (Test Mode) Normal operation
-# bit8: 0, (Reset DLL) Normal operation
-# bit11-9: 0, Write recovery for auto-precharge (3 required ??)
-# bit12: 0, Fast Active power down exit time (0 required)
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
-# bit0: 0, DRAM DLL enabled
-# bit1: 0, DRAM drive strength normal
-# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
-# bit5-3: 0 required
-# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
-# bit9-7: 0 required
-# bit10: 0, differential DQS enabled
-# bit11: 0 required
-# bit12: 0, DRAM output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 0x7 required
-# bit3: 1, MBUS Burst Chop disabled
-# bit6-4: 0x7 required
-# bit7: 0 required
-# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9: 0, no half clock cycle addition to dataout
-# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11: 0, 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 0xf required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
-# bit3-0: 0 required
-# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
-# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
-# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
-# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
-# bit31-20: 0 required
-
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
-# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
-# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
-# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
-# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
-# bit31-16: 0 required
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 0x0, CS0 hit selected
-# bit23-4: 0xfffff required
-# bit31-24: 0x0f, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 1, CS1 hit selected
-# bit23-4: 0xfffff required
-# bit31-24: 0x0f, Size (i.e. 256MB)
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
-# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
-# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
-# bit15-8: 0 required
-# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
-# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
-# bit31-24: 0 required
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
-# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
-# bit31-4 0 required
-
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
-# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
-# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
-# bit9-8: 0, Internal ODT assertion is controlled by fiels
-# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
-# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
-# bit14: 1, M_STARTBURST_IN ODT enabled
-# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
-# bit20-16: 0, Pad N channel driving strength for ODT
-# bit25-21: 0, Pad P channel driving strength for ODT
-# bit31-26: 0 required
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-# bit0: 1, enable DDR init upon this register write
-# bit31-1: 0, required
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/d-link/dnskw/Makefile b/board/d-link/dnskw/Makefile
new file mode 100644
index 0000000..85cebf7
--- /dev/null
+++ b/board/d-link/dnskw/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2011
+# Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dnskw.o
diff --git a/board/d-link/dnskw/dnskw.c b/board/d-link/dnskw/dnskw.c
new file mode 100644
index 0000000..22b0ffb
--- /dev/null
+++ b/board/d-link/dnskw/dnskw.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+#include "dnskw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* Gpio configuration */
+ kw_config_gpio(DNSKW_OE_VAL_LOW, DNSKW_OE_VAL_HIGH,
+ DNSKW_OE_LOW, DNSKW_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_SATA1_ACTn, /* sata1(left) status led */
+ MPP21_SATA0_ACTn, /* sata0(right) status led */
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO, /* power off out */
+ MPP25_GPIO,
+ MPP26_GPIO, /* power led */
+ MPP27_GPIO, /* sata0(right) error led */
+ MPP28_GPIO, /* sata1(left) error led */
+ MPP29_GPIO, /* usb error led */
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO, /* power key */
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO, /* enable sata 0 */
+ MPP40_GPIO, /* enable sata 1 */
+ MPP41_GPIO, /* hdd0 present */
+ MPP42_GPIO, /* hdd1 present */
+ MPP43_GPIO, /* usb status led */
+ MPP44_GPIO, /* fan status */
+ MPP45_GPIO, /* fan high speed */
+ MPP46_GPIO, /* fan low speed */
+ MPP47_GPIO, /* usb umount */
+ MPP48_GPIO, /* factory reset */
+ MPP49_GPIO, /* thermal sensor */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ kw_gpio_set_blink(DNSKW_GPIO_LED_POWER , 1);
+
+ kw_gpio_set_value(DNSKW_GPIO_SATA0_EN , 1);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..(%s) could not read PHY dev address\n", __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ debug("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/d-link/dnskw/dnskw.h b/board/d-link/dnskw/dnskw.h
new file mode 100644
index 0000000..8d2e2b1
--- /dev/null
+++ b/board/d-link/dnskw/dnskw.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DNSKW_H
+#define __DNSKW_H
+
+/* GPIO configuration */
+#define DNSKW_OE_LOW 0x00000000
+#define DNSKW_OE_HIGH 0x00039604
+
+#define DNSKW_GPIO_LED_POWER 26
+#define DNSKW_GPIO_SATA0_EN 39
+#define DNSKW_GPIO_SATA1_EN 40
+
+/* DNS-325 specific configuration */
+#ifdef CONFIG_BOARD_IS_DNS325
+#define DNSKW_OE_VAL_LOW 0x38000000 /* disable leds */
+#define DNSKW_OE_VAL_HIGH 0x00000800 /* disable leds */
+#endif /* CONFIG_BOARD_IS_DNS325 */
+
+/* PHY related */
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __DNSKW_H */
diff --git a/board/d-link/dnskw/kwbimage.dns325.cfg b/board/d-link/dnskw/kwbimage.dns325.cfg
new file mode 100644
index 0000000..b69c1df
--- /dev/null
+++ b/board/d-link/dnskw/kwbimage.dns325.cfg
@@ -0,0 +1,192 @@
+#
+# Copyright (C) 2011
+# Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30, 3120 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24: 1, enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
+# bit3-0: 0 required
+# bit4: 0, addr/cmd in smame cycle
+# bit5: 0, clk is driven during self refresh, we don't care for APX
+# bit6: 0, use recommended falling edge of clk for addr/cmd
+# bit11-7: 0 required
+# bit12: 1 required
+# bit13: 1 required
+# bit14: 0, input buffer always powered up
+# bit17-15: 0 required
+# bit18: 1, cpu lock transaction enabled
+# bit19: 0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
+# bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
+# bit7-4: 5, 6 cycle tRCD
+# bit11-8: 4, 5 cyle tRP
+# bit15-12: 5, 6 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20: 1, 18 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 2, 3 cycle tRRD
+# bit31-28: 2, 3 cyle tRTP
+
+DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
+# bit6-0: 0x33, 33 cycle tRFC
+# bit8-7: 0, 1 cycle tR2R
+# bit10-9: 0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+DATA 0xFFD01410 0x0000000c # DDR Address Control
+# bit1-0: 0, Cs0width=x8
+# bit3-2: 3, Cs0size=1Gb
+# bit5-4: 0, Cs1width=nonexistent
+# bit7-6: 0, Cs1size=nonexistent
+# bit9-8: 0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0, Cmd=Normal SDRAM Mode
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, Burst Length (2 required)
+# bit3: 0, Burst Type (0 required)
+# bit6-4: 5, CAS Latency (CL) 5
+# bit7: 0, (Test Mode) Normal operation
+# bit8: 0, (Reset DLL) Normal operation
+# bit11-9: 0, Write recovery for auto-precharge (3 required ??)
+# bit12: 0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DRAM DLL enabled
+# bit1: 0, DRAM drive strength normal
+# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
+# bit5-3: 0 required
+# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
+# bit9-7: 0 required
+# bit10: 0, differential DQS enabled
+# bit11: 0 required
+# bit12: 0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 0x7 required
+# bit3: 1, MBUS Burst Chop disabled
+# bit6-4: 0x7 required
+# bit7: 0 required
+# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0, no half clock cycle addition to dataout
+# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
+# bit3-0: 0 required
+# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
+# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 1, CS1 hit selected
+# bit23-4: 0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8: 0 required
+# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
+# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
+# bit31-24: 0 required
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4 0 required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
+# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
+# bit9-8: 0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT enabled
+# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit0: 1, enable DDR init upon this register write
+# bit31-1: 0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/boards.cfg b/boards.cfg
index a58efd6..ef73f76 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -163,7 +163,7 @@ Active arm arm926ejs davinci omicron calimain
Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael at walle.cc>
Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael at walle.cc>
Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy at gmail.com>
-Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
+Active arm arm926ejs kirkwood d-link dnskw dns325 dnskw:BOARD_IS_DNS325 Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka at openwrt.org>
Active arm arm926ejs kirkwood karo tk71 tk71 - -
Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp at keymile.com>
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
deleted file mode 100644
index 96db44f..0000000
--- a/include/configs/dns325.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_DNS325_H
-#define _CONFIG_DNS325_H
-
-/*
- * Machine number definition
- */
-#define MACH_TYPE_DNS325 3800
-#define CONFIG_MACH_TYPE MACH_TYPE_DNS325
-#define CONFIG_IDENT_STRING "\nD-Link DNS-325"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KIRKWOOD /* SOC Family Name */
-#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_DATE
-#define CONFIG_SYS_MVFS
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_SYS_PROMPT
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_NETCONSOLE
-#endif
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif
-
-/*
- * RTC driver configuration
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif
-
-/*
- * Enable GPI0 support
- */
-#define CONFIG_KIRKWOOD_GPIO
-
-/*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Console configuration
- */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
- * Enable device tree support
- */
-#define CONFIG_OF_LIBFDT
-
-/*
- * Display cpu info at boot
- */
-#define CONFIG_DISPLAY_CPUINFO
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
-#define CONFIG_ENV_ADDR 0xe0000
-#define CONFIG_ENV_OFFSET 0xe0000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define MTDIDS_DEFAULT "nand0=orion_nand"
-
-#define MTDPARTS_DEFAULT "mtdparts=orion_nand:" \
- "896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "loadaddr=0x800000\0" \
- "autoload=no\0" \
- "console=ttyS0,115200\0" \
- "mtdparts="MTDPARTS_DEFAULT \
- "optargs=\0" \
- "bootenv=uEnv.txt\0" \
- "importbootenv=echo Importing environment ...; " \
- "env import -t ${loadaddr} ${filesize}\0" \
- "loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \
- "setbootargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "${mtdparts} " \
- "root=${bootenvroot} " \
- "rootfstype=${bootenvrootfstype}\0" \
- "subbootcmd=run setbootargs; " \
- "if run bootenvloadimage; then " \
- "bootm ${loadaddr};" \
- "fi;\0" \
- "nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \
- "nandrootfstype=ubifs\0" \
- "nandloadimage=nand read ${loadaddr} kernel\0" \
- "setnandbootenv=echo Booting from nand ...; " \
- "setenv bootenvroot ${nandroot}; " \
- "setenv bootenvrootfstype ${nandrootfstype}; " \
- "setenv bootenvloadimage ${nandloadimage}\0"
-
-#define CONFIG_BOOTCOMMAND \
- "if test -n ${bootenv} && usb start; then " \
- "if run loadbootenv; then " \
- "echo Loaded environment ${bootenv} from usb;" \
- "run importbootenv;" \
- "fi;" \
- "if test -n ${bootenvcmd}; then " \
- "echo Running bootenvcmd ...;" \
- "run bootenvcmd;" \
- "fi;" \
- "fi;" \
- "run setnandbootenv subbootcmd;"
-
-#endif /* _CONFIG_DNS325_H */
diff --git a/include/configs/dnskw.h b/include/configs/dnskw.h
new file mode 100644
index 0000000..b415216
--- /dev/null
+++ b/include/configs/dnskw.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_DNSKW_H
+#define _CONFIG_DNSKW_H
+
+/*
+ * Machine number definition
+ */
+#ifdef CONFIG_BOARD_IS_DNS325
+#define MACH_TYPE_DNS325 3800
+#define CONFIG_MACH_TYPE MACH_TYPE_DNS325
+#define CONFIG_IDENT_STRING "\nD-Link DNS-325"
+
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.dns325.cfg
+
+#endif /* CONFIG_BOARD_IS_DNS325 */
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD /* SOC Family Name */
+#define CONFIG_KW88F6281 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_SYS_MVFS
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_SYS_PROMPT
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_NETCONSOLE
+#endif
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif
+
+/*
+ * RTC driver configuration
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Console configuration
+ */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Display cpu info at boot
+ */
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
+#define CONFIG_ENV_ADDR 0xe0000
+#define CONFIG_ENV_OFFSET 0xe0000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define MTDIDS_DEFAULT "nand0=orion_nand"
+
+#define MTDPARTS_DEFAULT "mtdparts=orion_nand:" \
+ "896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "loadaddr=0x800000\0" \
+ "autoload=no\0" \
+ "console=ttyS0,115200\0" \
+ "mtdparts="MTDPARTS_DEFAULT \
+ "optargs=\0" \
+ "bootenv=uEnv.txt\0" \
+ "importbootenv=echo Importing environment ...; " \
+ "env import -t ${loadaddr} ${filesize}\0" \
+ "loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \
+ "setbootargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "${mtdparts} " \
+ "root=${bootenvroot} " \
+ "rootfstype=${bootenvrootfstype}\0" \
+ "subbootcmd=run setbootargs; " \
+ "if run bootenvloadimage; then " \
+ "bootm ${loadaddr};" \
+ "fi;\0" \
+ "nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \
+ "nandrootfstype=ubifs\0" \
+ "nandloadimage=nand read ${loadaddr} kernel\0" \
+ "setnandbootenv=echo Booting from nand ...; " \
+ "setenv bootenvroot ${nandroot}; " \
+ "setenv bootenvrootfstype ${nandrootfstype}; " \
+ "setenv bootenvloadimage ${nandloadimage}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "if test -n ${bootenv} && usb start; then " \
+ "if run loadbootenv; then " \
+ "echo Loaded environment ${bootenv} from usb;" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n ${bootenvcmd}; then " \
+ "echo Running bootenvcmd ...;" \
+ "run bootenvcmd;" \
+ "fi;" \
+ "fi;" \
+ "run setnandbootenv subbootcmd;"
+
+#endif /* _CONFIG_DNSKW_H */
--
2.0.0.rc2
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