[U-Boot] [PATCH v3] powerpc/t4rdb: Add alternate serdes protocols to align with A-007186

[York Sun]

On 05/19/2014 10:34 PM, Chunhe Lan wrote:
> A-007186: SerDes PLL is calibrated at reset. It is possible
> for jitter to increase and cause the PLL to unlock when the
> temperature delta from the time the PLL is calibrated exceeds
> +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
> XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
> only using Ring VCOs are impacted.
> 
> Workaround:
> For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
> VCO, this need to use alternate serdes protocols. Alternate
> option has the same functionality as the original option; the
> only difference being LC VCO rather than Ring VCO.
> 
> Signed-off-by: Chunhe Lan <Chunhe.Lan at freescale.com>
> ---


Applied to u-boot-mpc85xx. Sorry for the late notice.

York