[U-Boot] [PATCH v4 6/6] Exynos: Split 5250 and 5420 memory bank configuration

[Akshay Saraswat]

From: Michael Pratt <mpratt at chromium.org>

Since snow has a different memory configuration than peach, split the
configuration between the 5250 and 5420. Exynos 5420 supports runtime
memory configuration detection, and can make the determination between 4
and 7 banks at runtime.

Include the bank size with the number of banks for context to make the
number of banks meaningful.

Signed-off-by: Michael Pratt <mpratt at chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s at samsung.com>
Acked-by: Simon Glass <sjg at chromium.org>
Tested-by: Simon Glass <sjg at chromium.org>
---
Changes since v3:
	- Introduced to this patch-set.
Changes since v2:
	- Added "Acked-by" & "Tested-by".
Changes since v1:
	- New patch.

 include/configs/exynos5-dt.h    | 2 --
 include/configs/exynos5250-dt.h | 5 +++++
 include/configs/exynos5420.h    | 4 ++++
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index 3c51650..e36a031 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -161,8 +161,6 @@
 
 #define CONFIG_RD_LVL
 
-#define CONFIG_NR_DRAM_BANKS	8
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 3982010..74e72a5 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -65,4 +65,9 @@
 #define LCD_YRES			1600
 #define LCD_BPP			LCD_COLOR16
 #endif
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
 #endif  /* __CONFIG_5250_H */
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h
index 2ffe5ee..d2a9556 100644
--- a/include/configs/exynos5420.h
+++ b/include/configs/exynos5420.h
@@ -45,4 +45,8 @@
  */
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
 
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	7
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
 #endif	/* __CONFIG_EXYNOS5420_H */
-- 
1.7.12.4