[U-Boot] [PATCH] powerpc/ifc: fix invalid CSn FTIM2.TCH setting

[shh.xie at gmail.com]

From: Shaohui Xie <Shaohui.Xie at freescale.com>

On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.

Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
---
based on 'next' of git://git.denx.de/u-boot-mpc85xx.git.

 include/configs/B4860QDS.h   | 2 +-
 include/configs/BSC9132QDS.h | 2 +-
 include/configs/C29XPCIE.h   | 2 +-
 include/configs/P1010RDB.h   | 2 +-
 include/configs/T104xRDB.h   | 2 +-
 include/configs/T208xRDB.h   | 2 +-
 include/configs/T4240QDS.h   | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 1af9ba6..43c9df0 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -340,7 +340,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 7bb5d33..49c16af 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -354,7 +354,7 @@ combinations. this should be removed later
 #define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3		0x0
 #endif
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 9e12fac..0dd1560 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -319,7 +319,7 @@
 #define CONFIG_SYS_CS2_FTIM1	(FTIM1_GPCM_TACO(0x0e) | \
 				FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2	(FTIM2_GPCM_TCS(0x0e) | \
-				FTIM2_GPCM_TCH(0x0) | \
+				FTIM2_GPCM_TCH(0x8) | \
 				FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3	0x0
 
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index d612a8b..50529bf 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -537,7 +537,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 8d6c51b..40bfc60 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -286,7 +286,7 @@
 #define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3		0x0
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 3a1c49c..5d10ad2 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -283,7 +283,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3		0x0
 
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index a770dd0..efdb68b 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
-- 
1.8.0