[U-Boot] [PATCH] driver/ddr: Fix DDR register timing_cfg_8

[York Sun]

The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun at freescale.com>
---
 drivers/ddr/fsl/ctrl_regs.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index dcf6287..04e4178 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
 
 	acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
 	wrtord_bg = max(4, picos_to_mclk(7500));
+	if (popts->otf_burst_chop_en)
+		wrtord_bg += 2;
+
 	pre_all_rec = 0;
 
 	ddr->timing_cfg_8 = (0
-- 
1.7.9.5