[U-Boot] [PATCH] board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config

[York Sun]

On 02/28/2014 12:48 AM, Prabhakar Kushwaha wrote:
> With the default value of MDIO_CLK_DIV generatee MDC is too high and It is
> violating the IEEE specs much higher than 2.5Mhz.
> 
> Although there is errata(A-006260) for EMI2(MDIO2), but same errata is
> been hit on EMI1(MDIO1). unfortunately this errata never hit on B4 rev1.
> So reduced the MDIO_CLK_DIV value.
> 

Please fix the typo and some grammar error in the commit message.
What is about B4 Rev 1? We support rev 2 and later in this u-boot.

York