[U-Boot] [PATCH 3/7][v3] powerpc:Add support of SPL non-relocation

[Prabhakar Kushwaha]

Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.

To avoid relocation:
	- Move bss_section within SPL range
	- Modify relocate_code()

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
 Changes for v2: Sending as it is
 Changes for v3: Sending as it is

 README                                  |    3 +++
 arch/powerpc/cpu/mpc85xx/start.S        |    2 ++
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |   12 ++++++++++++
 3 files changed, 17 insertions(+)

diff --git a/README b/README
index 216f0c7..413a844 100644
--- a/README
+++ b/README
@@ -3300,6 +3300,9 @@ FIT uImage format:
 		continuing (the hardware starts execution after just
 		loading the first page rather than the full 4K).
 
+		CONFIG_SPL_SKIP_RELOCATE
+		Avoid SPL relocation
+
 		CONFIG_SPL_NAND_BASE
 		Include nand_base.c in the SPL.  Requires
 		CONFIG_SPL_NAND_DRIVERS.
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 67e071b..c654363 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1645,6 +1645,7 @@ relocate_code:
 	mr	r10,r5		/* Save copy of Destination Address	*/
 
 	GET_GOT
+#ifndef CONFIG_SPL_SKIP_RELOCATE
 	mr	r3,r5				/* Destination Address	*/
 	lis	r4,CONFIG_SYS_MONITOR_BASE at h		/* Source      Address	*/
 	ori	r4,r4,CONFIG_SYS_MONITOR_BASE at l
@@ -1735,6 +1736,7 @@ relocate_code:
 
 	mtlr	r0
 	blr				/* NEVER RETURNS! */
+#endif
 	.globl	in_ram
 in_ram:
 
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 4fad68b..8453f3a 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,6 +57,16 @@ SECTIONS
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
+#ifdef CONFIG_SPL_SKIP_RELOCATE
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : {
+		*(.sbss*)
+		*(.bss*)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+#endif
 
 /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
 #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
@@ -86,6 +96,7 @@ SECTIONS
 	} = 0xffff
 #endif
 
+#ifndef CONFIG_SPL_SKIP_RELOCATE
 	/*
 	 * Make sure that the bss segment isn't linked at 0x0, otherwise its
 	 * address won't be updated during relocation fixups.
@@ -100,4 +111,5 @@ SECTIONS
 	}
 	. = ALIGN(4);
 	__bss_end = .;
+#endif
 }
-- 
1.7.9.5