[U-Boot] Embest Marsboard
Stefano Babic
sbabic at denx.de
Wed Mar 12 11:18:40 CET 2014
Hi Ben,
On 10/03/2014 20:51, Ben Hewson wrote:
> Hello all,
>
> This is my first post here or any mailing list, so my apologies for any
> mistakes.
>
Do not worry ;-)
> I have added board support for the Embest Marsboard based on the imx6 dual
> core chip. Embest do provide an old version of U-Boot ( 2009.08-svn8 ).
>
> Using the current git master branch and the Wandboard and Boundry Nitrogen6x
> and the original Marsboard files I have a working U-Boot. Both the eMMC and SD
> card and SPI flash environment appear to be working. I seem to have problems
> with networking, but have discovered the same problem with the original U-Boot
> so could be my network cable.
>
> Here are the changes from the current git master.
>
Please use git send-email to post patches to the ML. This avoids that
your mailer damages the patches.
Take also a look at the great Simon's patman tool in tool/patman. The
README in that directory explains very well how to use it. Posting
patches to ML is much more easier with this tool.
I appreciate the description of the patches, but this must separate from
the commit message. At the best, write a cover (again, patman will help
you) letting in the patches only the description of what the patch is
supposed to add or to fix.
>
> Date: Sat, 22 Feb 2014 12:48:06 +0000
> Subject: [PATCH 1/3] add entry for Embest imx6 Marsboard
>
> ---
> boards.cfg | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/boards.cfg b/boards.cfg
> index c90bb2b..d537b61 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -294,6 +294,7 @@ Active arm armv7 mx5 genesi
> mx51_efikamx
> Active arm armv7 mx5 genesi mx51_efikamx
> mx51_efikasb
> mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
> -
> Active arm armv7 mx5 ttcontrol vision2
> vision2
> vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
> Stefano Babic <sbabic at denx.de>
> Active arm armv7 mx6 - udoo
> udoo_quad
> udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024
> Fabio Estevam <fabio.estevam at freescale.com>
> +Active arm armv7 mx6 embest mx6q_marsboard
> mx6q_marsboard
We need the maintainer for the board - add your name and e-mail address
here.
>
> Date: Mon, 10 Mar 2014 18:32:53 +0000
> Subject: [PATCH 2/3] marsboard target files
>
> ---
> board/embest/mx6q_marsboard/Makefile | 7 +
> board/embest/mx6q_marsboard/mx6q_marsboard.c | 653
> +++++++++++++++++++++++++++
> include/configs/mx6q_marsboard.h | 418 +++++++++++++++++
> 3 files changed, 1078 insertions(+)
> create mode 100644 board/embest/mx6q_marsboard/Makefile
> create mode 100644 board/embest/mx6q_marsboard/mx6q_marsboard.c
> create mode 100644 include/configs/mx6q_marsboard.h
>
> diff --git a/board/embest/mx6q_marsboard/Makefile
> b/board/embest/mx6q_marsboard/Makefile
> new file mode 100644
> index 0000000..c4eb0e9
> --- /dev/null
> +++ b/board/embest/mx6q_marsboard/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# (C) Copyright 2013 Freescale Semiconductor, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
This is ok - SPDX Licence reference.
> +
> +obj-y := mx6q_marsboard.o
> diff --git a/board/embest/mx6q_marsboard/mx6q_marsboard.c
> b/board/embest/mx6q_marsboard/mx6q_marsboard.c
> new file mode 100644
> index 0000000..5f39af8
> --- /dev/null
> +++ b/board/embest/mx6q_marsboard/mx6q_marsboard.c
> @@ -0,0 +1,653 @@
> +/*
> + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
This is not ok. Do not add the full header, simply use SPDX as before.
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sys_proto.h>
> +#include <malloc.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/errno.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/imx-common/sata.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <linux/fb.h>
> +#include <ipu_pixfmt.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/mxc_hdmi.h>
> +#include <i2c.h>
> +
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
> +
> +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
> + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
> +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> +
> +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
> +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +
> +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> + PAD_CTL_SRE_SLOW)
> +
> +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
> +
> +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
> +
> +
> +
> +#ifdef CONFIG_ARCH_MMU
> +#include <asm/mmu.h>
> +#include <asm/arch/mmu.h>
> +#endif
ARCH_MMU ? Please check all FSL's U-Boot defines that are not used in
mainline, and drop them.
> +
> +
> +#ifdef CONFIG_IMX_UDC
> +#include <usb/imx_udc.h>
> +#endif
CONFIG_IMX_UDC ??
> +
> +#ifdef CONFIG_ANDROID_RECOVERY
CONFIG_ANDROID_RECOVERY ?? Please cleanup.
> +#include "../common/recovery.h"
> +#include <part.h>
> +#include <ext2fs.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/partitions.h>
> +#include <ubi_uboot.h>
> +#include <jffs2/load_kernel.h>
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static u32 system_rev;
> +//static enum boot_device boot_dev;
No dead code. And no C++ comments.
> +
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> + /* 4 bit bus width */
> + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
> + {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
> + {NULL, 0},
> +};
> +#endif
> +
> +u32 get_board_rev(void)
> +{
> +
> + system_rev = 0x63000;
> +
> + return system_rev;
> +}
No. Set CONFIG_REVISION_TAG, instead. The default get_board_rev() in
arch/arm/cpu/armv7/mx6/soc.c already reports the SOC version.
> +
> +int dram_init(void)
> +{
> + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
> +
Better: use get_ram_size() to find dynamically the size of the supplied
RAM. See for example the mx6sabre* boards.
> + return 0;
> +}
> +
> +iomux_v3_cfg_t const uart1_pads[] = {
> + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart2_pads[] = {
> + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +struct i2c_pads_info i2c_pad_info2 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
> + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
> + .gp = IMX_GPIO_NR(1, 5)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
> + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
> + .gp = IMX_GPIO_NR(7, 11)
> + }
> +};
> +
> +
> +static void setup_iomux_uart(void)
> +{
> +
> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
> +
> + /* UART1 TXD */
> + //mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT6__UART1_TXD);
No dead code, this must be fixed globally,
> +
> + /* UART1 RXD */
> + //mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT7__UART1_RXD);
> +
> + /* UART2 TXD */
> + //mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
> +
> + /* UART2 RXD */
> + //mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
> +}
> +
> +
> +#ifdef CONFIG_MXC_SPI
> +iomux_v3_cfg_t const ecspi1_pads[] = {
> + /* SS1 */
> + MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +};
> +
> +void setup_spi(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
> + ARRAY_SIZE(ecspi1_pads));
> +}
> +#endif
> +
> +
> +#ifdef CONFIG_MXC_SPI_not_used
_not_used ???
> +s32 spi_get_cfg(struct imx_spi_dev_t *dev)
> +{
> + switch (dev->slave.cs) {
> + case 0:
> + /* SPI-NOR */
> + dev->base = ECSPI1_BASE_ADDR;
> + dev->freq = 25000000;
> + dev->ss_pol = IMX_SPI_ACTIVE_LOW;
> + dev->ss = 0;
> + dev->fifo_sz = 64 * 4;
> + dev->us_delay = 0;
> + break;
> + case 1:
> + /* SPI-NOR */
> + dev->base = ECSPI1_BASE_ADDR;
> + dev->freq = 25000000;
> + dev->ss_pol = IMX_SPI_ACTIVE_LOW;
> + dev->ss = 1;
> + dev->fifo_sz = 64 * 4;
> + dev->us_delay = 0;
> + break;
> + default:
> + printf("Invalid Bus ID!\n");
> + }
> +
> + return 0;
> +}
> +
> +void spi_io_init(struct imx_spi_dev_t *dev)
> +{
> + switch (dev->base) {
> + case ECSPI1_BASE_ADDR:
> + /* SCLK */
> + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D16__ECSPI1_SCLK);
> +
> + /* MISO */
> + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D17__ECSPI1_MISO);
> +
> + /* MOSI */
> + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D18__ECSPI1_MOSI);
> +
> + if (dev->ss == 1)
> + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D19__ECSPI1_SS1);
> + else if(dev->ss == 0)
> + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_EB2__ECSPI1_SS0);
> + break;
> + case ECSPI2_BASE_ADDR:
> + case ECSPI3_BASE_ADDR:
> + /* ecspi2-3 fall through */
> + break;
> + default:
> + break;
> + }
> +}
> +#endif
If this is not used, drop it !
> +
> +
> +iomux_v3_cfg_t const enet_pads1[] = {
> + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +
> + MX6_PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +
> + /* pin 42 PHY nRST */
> + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +
> +};
> +
> +iomux_v3_cfg_t const enet_pads2[] = {
> + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +static void setup_iomux_enet(void)
> +{
> + /* phy reset: gpio3-31 */
> + gpio_direction_output(IMX_GPIO_NR(3,31), 0);
> +
> + gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
> + gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
> + gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
> + gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
> + gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
> + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
> + gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
> +
> + udelay(1000 * 10);
> +
> + gpio_direction_output(IMX_GPIO_NR(3,31), 1);
> +
> + imx_iomux_v3_setup_multiple_pads(enet_pads2,ARRAY_SIZE(enet_pads2));
> +
> +
> +
No too much empty lines.
> +
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + uint32_t base = IMX_FEC_BASE;
> + struct mii_dev *bus = NULL;
> + struct phy_device *phydev = NULL;
> + int ret;
> +
> + setup_iomux_enet();
> +
> +#ifdef CONFIG_FEC_MXC
> + bus = fec_get_miibus(base, -1);
> + if (!bus)
> + return 0;
> + /* scan phy 4,5,6,7 */
> + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
> + if (!phydev) {
> + free(bus);
> + return 0;
> + }
> + printf("using phy at %d\n", phydev->addr);
> + ret = fec_probe(bis, -1, base, bus, phydev);
> + if (ret) {
> + printf("FEC MXC: %s:failed\n", __func__);
> + free(phydev);
> + free(bus);
> + }
> +#endif
> +
> +#ifdef CONFIG_CI_UDC
> + /* For otg ethernet*/
> + usb_eth_initialize(bis);
> +#endif
> + return 0;
> +}
> +
> +#ifdef CONFIG_CMD_MMC
> +
> +struct fsl_esdhc_cfg usdhc_cfg[2] = {
> + {USDHC2_BASE_ADDR},
> + {USDHC3_BASE_ADDR},
> +};
> +
> +#ifdef CONFIG_DYNAMIC_MMC_DEVNO
????
> +int get_mmc_env_devno(void)
> +{
> + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
> +
> + /* BOOT_CFG2[3] and BOOT_CFG2[4] */
> + return (soc_sbmr & 0x00001800) >> 11;
> +}
> +#endif
> +
> +iomux_v3_cfg_t mx6q_usdhc1_pads[] = {
> + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t mx6q_usdhc2_pads[] = {
> + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t mx6q_usdhc3_pads[] = {
> + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t mx6q_usdhc4_pads[] = {
> + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret;
> +
> + if (cfg->esdhc_base == USDHC2_BASE_ADDR) {
> + gpio_direction_input(IMX_GPIO_NR(1, 4));
> + ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
> + } else {
> + // eMMC has no CD
> + ret = 1;
> + }
> +
> + return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + s32 status = 0;
> + u32 index = 0;
> +
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> +
> + usdhc_cfg[0].max_bus_width = 4;
> + usdhc_cfg[1].max_bus_width = 4;
> +
> + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; index++) {
> + switch (index) {
> + case 0:
> + imx_iomux_v3_setup_multiple_pads(
> + mx6q_usdhc2_pads, ARRAY_SIZE(mx6q_usdhc2_pads));
> +
> + break;
> + case 1:
> + imx_iomux_v3_setup_multiple_pads(
> + mx6q_usdhc3_pads, ARRAY_SIZE(mx6q_usdhc3_pads));
> + break;
Wait: you set up two USDHC controllers, but you set the pinmux also for
usdhc3 and usdhc4.
> + default:
> + printf("Warning: you configured more USDHC controllers"
> + "(%d) then supported by the board (%d)\n",
> + index + 1, CONFIG_SYS_FSL_USDHC_NUM);
> + return status;
> + }
> + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
> + }
> +
> + return status;
> +}
> +
> +
> +/* For DDR mode operation, provide target delay parameter for each SD port.
Wrong multi-line comment style.
> + * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
> + * is dependent on signal layout for that particular port. If the following
> + * CONFIG is not defined, then the default target delay value will be used.
> + */
> +#ifdef CONFIG_GET_DDR_TARGET_DELAY
??????
> +u32 get_ddr_delay(struct fsl_esdhc_cfg *cfg)
> +{
> + /* No delay required */
> + return 0;
> +}
> +#endif
> +
> +#endif
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> +
> + gpio_direction_output(GP_USB_OTG_PWR, 1); /* OTG power off - was 0 here */
What should the comment explain ? Is OTG off or on ?
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + struct iomuxc_base_regs *const iomuxc_regs
> + = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
> +
> + clrsetbits_le32(&iomuxc_regs->gpr[1],
> + IOMUXC_GPR1_OTG_ID_MASK,
> + IOMUXC_GPR1_OTG_ID_GPIO1);
> +
> +
> + /* board id for linux */
> + gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
> +
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> +
> +
> +#ifdef CONFIG_MXC_SPI
> + setup_spi();
> +#endif
> +
> +#ifdef CONFIG_I2C_MXC
> + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
> +#endif
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_ANDROID_RECOVERY
????
> +struct reco_envs supported_reco_envs[BOOT_DEV_NUM] = {
> + {
> + .cmd = NULL,
> + .args = NULL,
> + },
> + {
> + .cmd = NULL,
> + .args = NULL,
> + },
> + {
> + .cmd = NULL,
> + .args = NULL,
> + },
> + {
> + .cmd = NULL,
> + .args = NULL,
> + },
> + {
> + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC,
> + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC,
> + },
> + {
> + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC,
> + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC,
> + },
> + {
> + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC,
> + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC,
> + },
> + {
> + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC,
> + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC,
> + },
> + {
> + .cmd = NULL,
> + .args = NULL,
> + },
> +};
> +
> +int check_recovery_cmd_file(void)
> +{
> + int button_pressed = 0;
> + int recovery_mode = 0;
> + u32 reg;
> +
> + recovery_mode = check_and_clean_recovery_flag();
> +
> + /* Check Recovery Combo Button press or not. */
> + mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_19__GPIO_4_5);
> + reg = readl(GPIO4_BASE_ADDR + GPIO_GDIR);
> + reg &= ~(1<<5);
> + writel(reg, GPIO4_BASE_ADDR + GPIO_GDIR);
> + reg = readl(GPIO4_BASE_ADDR + GPIO_PSR);
> + if (!(reg & (1 << 5))) { /* VOL_DN key is low assert */
> + button_pressed = 1;
> + printf("Recovery key pressed\n");
> + }
> +
> + return recovery_mode || button_pressed;
> +}
> +#endif
> +
> +int board_late_init(void)
> +{
> + return 0;
> +}
Not used - drop it.
> +
> +
> +int checkboard(void)
> +{
> + puts("Board: MX6Q-MARSBOARD\n");
> +
> + /*
> + switch (__REG(SRC_BASE_ADDR + 0x8)) {
> + case 0x0001:
> + printf("POR");
> + break;
> + case 0x0009:
> + printf("RST");
> + break;
> + case 0x0010:
> + case 0x0011:
> + printf("WDOG");
> + break;
> + default:
> + printf("unknown");
> + }
> + printf("]\n");
> + */
> +
> + /*
> + printf("Boot Device: ");
> + switch (get_boot_device()) {
> + case WEIM_NOR_BOOT:
> + printf("NOR\n");
> + break;
> + case ONE_NAND_BOOT:
> + printf("ONE NAND\n");
> + break;
> + case PATA_BOOT:
> + printf("PATA\n");
> + break;
> + case SATA_BOOT:
> + printf("SATA\n");
> + break;
> + case I2C_BOOT:
> + printf("I2C\n");
> + break;
> + case SPI_NOR_BOOT:
> + printf("SPI NOR\n");
> + break;
> + case SD_BOOT:
> + printf("SD\n");
> + break;
> + case MMC_BOOT:
> + printf("MMC\n");
> + break;
> + case NAND_BOOT:
> + printf("NAND\n");
> + break;
> + case UNKNOWN_BOOT:
> + default:
> + printf("UNKNOWN\n");
> + break;
> + }
> + */
> + return 0;
> +}
> +
This is all dead code, please drop it.
> +#ifdef CONFIG_IMX_UDC
?????
> +
> +void udc_pins_setting(void)
> +{
> +#define GPIO_3_22_BIT_MASK (1<<22)
> + u32 reg;
> + mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_1__USBOTG_ID);
> + /* USB_OTG_PWR */
> + mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D22__GPIO_3_22);
> +
> + reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
> + /* set gpio_3_22 as output */
> + reg |= GPIO_3_22_BIT_MASK;
> + writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
> +
> + /* set USB_OTG_PWR to 0 */
> + reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
> + reg &= ~GPIO_3_22_BIT_MASK;
> + writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
> +
> + mxc_iomux_set_gpr_register(1, 13, 1, 1);
> +}
> +#endif
> diff --git a/include/configs/mx6q_marsboard.h b/include/configs/mx6q_marsboard.h
> new file mode 100644
> index 0000000..80f02a4
> --- /dev/null
> +++ b/include/configs/mx6q_marsboard.h
> @@ -0,0 +1,418 @@
> +/*
> + * Copyright (C) 2012-2013 Embest Tech, Inc.
> + *
> + * Configuration settings for the MX6Q Marsboard.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include "mx6_common.h"
> +#include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/gpio.h>
> +#include <asm/sizes.h>
> +
> + /* High Level Configuration Options */
> +#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
> +#define CONFIG_MXC
> +#define CONFIG_MX6
> +#define CONFIG_MX6Q_MARSBOARD
> +#define CONFIG_FLASH_HEADER
> +#define CONFIG_FLASH_HEADER_OFFSET 0x400
> +#define CONFIG_MX6_CLK32 32768
No. Please check with supported boards in mainline. This is a cut&paste
from FSL's 2009.08.
CONFIG_MX6Q_MARSBOARD us surely not required. I am expecting only
CONFIG_MX6.
> +
> +
> +#define MACH_TYPE_MX6Q_MARSBOARD 3770
> +#define CONFIG_MACH_TYPE MACH_TYPE_MX6Q_MARSBOARD
Drop MACH_TYPE_MX6Q_MARSBOARD (it is used only here), and simply
#define CONFIG_MACH_TYPE 3770
> +
> +#define CONFIG_SKIP_RELOCATE_UBOOT
??? wrong
> +
> +#define CONFIG_ARCH_CPU_INIT
> +#undef CONFIG_ARCH_MMU /* disable MMU first */
> +#define CONFIG_L2_OFF /* disable L2 cache first*/
All old stuff. L2 is working on MX6. Check with other boards.
> +
> +#define CONFIG_MX6_HCLK_FREQ 24000000
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define CONFIG_SYS_64BIT_VSPRINTF
> +
> +#define BOARD_LATE_INIT
Drop it.
> +
> +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> +#define CONFIG_REVISION_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
> +/* size in bytes reserved for initial data */
> +#define CONFIG_SYS_GBL_DATA_SIZE 128
No. GBL_DATA_SIZE is generated (GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_MXC_GPIO
> +//#define CONFIG_CI_UDC
Drop it, and then drop the code in board file.
> +#define CONFIG_USBD_HS
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_ETHER
> +#define CONFIG_USB_ETH_CDC
> +#define CONFIG_NETCONSOLE
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART2_BASE
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
> +
> +/***********************************************************
> + * Command definition
> + ***********************************************************/
> +
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_BOOTZ
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_ETHPRIME "FEC"
If there is only one interface, you do not need CONFIG_ETHPRIME
> +#define CONFIG_FEC_MXC_PHYADDR 6
> +#define CONFIG_PHYLIB
> +
> +#define CONFIG_NET_RETRY_COUNT 100
> +#define CONFIG_NET_MULTI 1
You do not need it anymore.
> +#define CONFIG_BOOTP_SUBNETMASK
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_DNS
> +
> +
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_IMXOTP
CONFIG_MXC_OCOTP.
> +
> +
> +/* Enable below configure when supporting nand */
Comment is wrong
> +
> +#define CONFIG_CMD_MMC
> +#define CONFIG_CMD_SF
> +//#define CONFIG_CMD_ENV
> +#define CONFIG_CMD_REGUL
> +
> +#define CONFIG_CMD_CLOCK
> +#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
> +
> +#define CONFIG_CMD_SATA
> +#undef CONFIG_CMD_IMLS
Put all command set together, it is easy to maintain.
> +
> +#define CONFIG_CMD_IMX_DOWNLOAD_MODE
?????
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_PRIME "FEC0"
> +
> +#define CONFIG_LOADADDR 0x12000000 /* loadaddr env var */
> +//#define CONFIG_RD_LOADADDR 0x11000000
> +#define CONFIG_SYS_TEXT_BASE 0x17800000 // ??
Why "//??" - CONFIG_SYS_TEXT_BASE is correct.
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=zImage\0" \
> + "console=ttymxc1\0" \
> + "splashpos=m,m\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "fdt_file=imx6q-marsboard.dtb\0" \
> + "fdt_addr=0x18000000\0" \
> + "boot_fdt=try\0" \
> + "ip_dyn=yes\0" \
> + "mmcdev=0\0" \
> + "mmcpart=1\0" \
> + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
> + "update_sd_firmware_filename=u-boot.imx\0" \
> + "update_sd_firmware=" \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "if mmc dev ${mmcdev}; then " \
> + "if ${get_cmd} ${update_sd_firmware_filename}; then " \
> + "setexpr fw_sz ${filesize} / 0x200; " \
> + "setexpr fw_sz ${fw_sz} + 1; " \
> + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
> + "fi; " \
> + "fi\0" \
> + "mmcargs=setenv bootargs console=${console},${baudrate} " \
> + "root=${mmcroot}\0" \
> + "loadbootscript=" \
> + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> + "bootscript=echo Running bootscript from mmc ...; " \
> + "source\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if run loadfdt; then " \
> + "bootz ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootz; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootz; " \
> + "fi;\0" \
> + "netargs=setenv bootargs console=${console},${baudrate} " \
> + "root=/dev/nfs " \
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> + "netboot=echo Booting from net ...; " \
> + "run netargs; " \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "${get_cmd} ${image}; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> + "bootz ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootz; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootz; " \
> + "fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "mmc dev ${mmcdev}; if mmc rescan; then " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loadimage; then " \
> + "run mmcboot; " \
> + "else run netboot; " \
> + "fi; " \
> + "fi; " \
> + "else run netboot; fi"
> +
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_PROMPT "MX6Q MARSBOARD U-Boot > "
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> +
> +#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
> +#define CONFIG_SYS_MEMTEST_END 0x10010000
> +
> +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_HZ 1000
> +
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
> +#ifdef CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#endif
> +
> +#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
> +#define CONFIG_FEC0_PINMUX -1
> +#define CONFIG_FEC0_MIIBASE -1
> +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
????
> +
> +#define CONFIG_MXC_FEC
> +#define CONFIG_FEC0_PHY_ADDR 4
The phy address was already defined.
> +#define CONFIG_ETH_PRIME
> +#define CONFIG_RMII
> +#define CONFIG_PHY_MICREL_KSZ9021
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_NET
Something went wrong here, ethernet was already set.
> +//#define CONFIG_IPADDR 192.168.1.103
Drop it !
> +
> +/*The IP ADDRESS of SERVERIP*/
> +//#define CONFIG_SERVERIP _SERVER_IP_ADDR_
> +
> +//#define CONFIG_NETMASK 255.255.255.0
> +
> +/*
> + * OCOTP Configs
> + */
> +#ifdef CONFIG_CMD_IMXOTP
> + #define CONFIG_IMX_OTP
> + #define IMX_OTP_BASE OCOTP_BASE_ADDR
> + #define IMX_OTP_ADDR_MAX 0x7F
> + #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
> +#endif
> +
> +/*
> + * I2C Configs
> + */
> +#ifdef CONFIG_CMD_I2C
> + #define CONFIG_SYS_I2C
> + #define CONFIG_SYS_I2C_MXC
> + #define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR
> + #define CONFIG_SYS_I2C_SPEED 100000
> + #define CONFIG_SYS_I2C_SLAVE 0x1f
> +#endif
> +
> +/*
> + * SPI Configs
> + */
> +#ifdef CONFIG_CMD_SF
> + #define CONFIG_SPI_FLASH
> + #define CONFIG_SPI_FLASH_SST
> + #define CONFIG_MXC_SPI
> + #define CONFIG_SF_DEFAULT_BUS 0
> + #define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(2, 30)<<8))
> + #define CONFIG_SF_DEFAULT_SPEED 25000000
> + #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
> +#endif
> +
> +/* Regulator Configs */
> +#ifdef CONFIG_CMD_REGUL
U-Boot has a PMIC framework. Drop this stuff and if you need to set the
regulators, use the framework.
> + #define CONFIG_ANATOP_REGULATOR
> + #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
> + #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
> +#endif
> +
> +/*
> + * MMC Configs
> + */
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +
> +#define CONFIG_MMC
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_BOUNCE_BUFFER
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +
> +#ifdef CONFIG_MX6Q
> +#define CONFIG_CMD_SATA
> +#endif
> +
> +/*
> + * SATA Configs
> + */
> +#ifdef CONFIG_CMD_SATA
> +#define CONFIG_DWC_AHSATA
> +#define CONFIG_SYS_SATA_MAX_DEVICE 1
> +#define CONFIG_DWC_AHSATA_PORT_ID 0
> +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
> +#define CONFIG_LBA48
> +#define CONFIG_LIBATA
> +#endif
> +
> +/*-----------------------------------------------------------------------
> + * Stack sizes
> + *
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
> +
> +/*-----------------------------------------------------------------------
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1
> +/*
> +#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
> +#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
> +#define iomem_valid_addr(addr, size) \
> + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
> +*/
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
You have definetely mix up old and new code. Please clean up before next
post.
> +
> +/*-----------------------------------------------------------------------
Wrong multiline comment
> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_NO_FLASH
> +
> +/* Monitor at beginning of flash */
> +/* #define CONFIG_FSL_ENV_IN_MMC */
> +/* #define CONFIG_FSL_ENV_IN_SATA */
Dead code.
> +#define CONFIG_FSL_ENV_IN_SF
> +
> +#define CONFIG_ENV_SECT_SIZE (8 * 1024)
> +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> +
> +#if defined(CONFIG_FSL_ENV_IN_NAND)
> + #define CONFIG_ENV_IS_IN_NAND 1
> + #define CONFIG_ENV_OFFSET 0x100000
> +#elif defined(CONFIG_FSL_ENV_IN_MMC)
> + #define CONFIG_ENV_IS_IN_MMC 1
> + #define CONFIG_ENV_OFFSET (768 * 1024)
> +#elif defined(CONFIG_FSL_ENV_IN_SATA)
> + #define CONFIG_ENV_IS_IN_SATA 1
> + #define CONFIG_SATA_ENV_DEV 0
> + #define CONFIG_ENV_OFFSET (768 * 1024)
> +#elif defined(CONFIG_FSL_ENV_IN_SF)
> + #define CONFIG_ENV_IS_IN_SPI_FLASH
> + #define CONFIG_ENV_OFFSET (768 * 1024)
> + #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
> + #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
> + #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
> + #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
> +
> +#else
> + #define CONFIG_ENV_IS_NOWHERE 1
> +#endif
> +#endif /* __CONFIG_H */
> -- 1.8.3.2 Date: Mon, 10 Mar 2014 18:48:16 +0000 Subject: [PATCH 3/3] sizes.h include path moved --- include/configs/mx6q_marsboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6q_marsboard.h b/include/configs/mx6q_marsboard.h index 80f02a4..d84fa1c 100644 --- a/include/configs/mx6q_marsboard.h +++ b/include/configs/mx6q_marsboard.h @@ -25,7 +25,7 @@ #include "mx6_common.h" #include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h> -#include <asm/sizes.h> +#include <linux/sizes.h> /* High Level Configuration Options */ #define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
> -- 1.8.3.2
Best regards,
Stefano Babic
--
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