[U-Boot] [RFC PATCH 6/6] fpga: xilinx: Simplify load/dump/info function handling

[Michal Simek]

On 03/14/2014 09:27 PM, Tom Rini wrote:
> On Thu, Mar 13, 2014 at 03:52:48PM +0100, Michal Simek wrote:
> 
>> Connect FPGA version with appropriate operations
>> to remove huge switch-cases for every FPGA family.
>> Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.
>>
>> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> 
> I like the concept.  Did you go through the u-boot.map files on
> spartan/etc to make sure we aren't discarding things now?  That'd be the
> follow up on compile testing the series.

Good that you like the concept - this was my intention for this RFC.
I will check it that's not a problem. Enough time to finish this
for the next release.

The next patch I want to do in fpga is to synchronize load/loadbitstream
commands.
The reason is that we need to add one more load which is
currently called loadfs which takes bitstream from filesystem
and load it with small chunks which are passed to programmable IP.
The whole reason is that system is working with limited amount
of memory that's why can't be done in 2 steps that fatload is called
and move bitstream to memory and then fpga load setup one DMA
to program it.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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