[U-Boot] [Patch v2 3/5] ARMv8/ls2100a_emu: Add LS2100A emulator board support

York Sun yorksun at freescale.com
Wed Mar 19 22:02:23 CET 2014


LS2100A is an ARMv8 implementation. This adds board support for emulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting

Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Arnab Basu <arnab.basu at freescale.com>
---
 board/freescale/ls2100a_emu/Makefile         |    8 +
 board/freescale/ls2100a_emu/README           |   16 ++
 board/freescale/{t4qds => ls2100a_emu}/ddr.c |   90 ++++++++---
 board/freescale/ls2100a_emu/ddr.h            |   57 +++++++
 board/freescale/ls2100a_emu/ls2100a_emu.c    |   56 +++++++
 boards.cfg                                   |    1 +
 include/configs/ls2100a_emu.h                |  205 ++++++++++++++++++++++++++
 7 files changed, 409 insertions(+), 24 deletions(-)
 create mode 100644 board/freescale/ls2100a_emu/Makefile
 create mode 100644 board/freescale/ls2100a_emu/README
 copy board/freescale/{t4qds => ls2100a_emu}/ddr.c (58%)
 create mode 100644 board/freescale/ls2100a_emu/ddr.h
 create mode 100644 board/freescale/ls2100a_emu/ls2100a_emu.c
 create mode 100644 include/configs/ls2100a_emu.h

diff --git a/board/freescale/ls2100a_emu/Makefile b/board/freescale/ls2100a_emu/Makefile
new file mode 100644
index 0000000..3fee04b
--- /dev/null
+++ b/board/freescale/ls2100a_emu/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls2100a_emu.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2100a_emu/README b/board/freescale/ls2100a_emu/README
new file mode 100644
index 0000000..9a8a618
--- /dev/null
+++ b/board/freescale/ls2100a_emu/README
@@ -0,0 +1,16 @@
+Freescale ls2100a_emu
+
+This is a emulator target with limited peripherals.
+
+Memory map from core's view
+
+0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/ls2100a_emu/ddr.c
similarity index 58%
copy from board/freescale/t4qds/ddr.c
copy to board/freescale/ls2100a_emu/ddr.c
index 7586cc3..4c16b3f 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/ls2100a_emu/ddr.c
@@ -1,18 +1,12 @@
 /*
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2014 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <asm/mmu.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -24,7 +18,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 
-	if (ctrl_num > 2) {
+	if (ctrl_num > 3) {
 		printf("Not supported controller number %d\n", ctrl_num);
 		return;
 	}
@@ -41,7 +35,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		pbsp = udimms[0];
 
 
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
 	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
 	ddr_freq = get_ddr_freq(0) / 1000000;
@@ -49,14 +43,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		if (pbsp->n_ranks == pdimm->n_ranks &&
 		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
 			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
 				popts->clk_adjust = pbsp->clk_adjust;
 				popts->wrlvl_start = pbsp->wrlvl_start;
 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -65,17 +55,13 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	}
 
 	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s\n"
+		printf("Error: board specific timing not found for data rate %lu MT/s\n"
 			"Trying to use the highest speed (%u) parameters\n",
 			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
@@ -111,17 +97,73 @@ found:
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 }
 
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 1073741824u,
+	.capacity = 2147483648,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 937,
+	.caslat_x = 0x6FC << 4,  /* 14,13,11,10,9,8,7,6 */
+	.taa_ps = 13090,
+	.twr_ps = 15000,
+	.trcd_ps = 13090,
+	.trrd_ps = 5000,
+	.trp_ps = 13090,
+	.tras_ps = 33000,
+	.trc_ps = 46090,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 25000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
 
-	puts("Initializing....using SPD\n");
+	puts("Initializing DDR....");
 
+	puts("using SPD\n");
 	dram_size = fsl_ddr_sdram();
 
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	puts("    DDR: ");
 	return dram_size;
 }
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].size = gd->ram_size -
+					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+	} else {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+	}
+}
diff --git a/board/freescale/ls2100a_emu/ddr.h b/board/freescale/ls2100a_emu/ddr.h
new file mode 100644
index 0000000..77f6aaf
--- /dev/null
+++ b/board/freescale/ls2100a_emu/ddr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  2140, 0, 4,     4, 0x0, 0x0},
+	{1,  2140, 0, 4,     4, 0x0, 0x0},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{4,  2140, 0, 5,     4, 0x0, 0x0},
+	{2,  2140, 0, 5,     4, 0x0, 0x0},
+	{1,  2140, 0, 4,     4, 0x0, 0x0},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/ls2100a_emu/ls2100a_emu.c b/board/freescale/ls2100a_emu/ls2100a_emu.c
new file mode 100644
index 0000000..608a88c
--- /dev/null
+++ b/board/freescale/ls2100a_emu/ls2100a_emu.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	init_final_memctl_regs();
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	init_early_memctl_regs();	/* tighten IFC timing */
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	printf("DRAM:  ");
+	gd->ram_size = initdram(0);
+
+	if (gd->ram_size > 0) {
+		print_size(gd->ram_size, "");
+		board_add_ram_info(0);
+		putc('\n');
+	}
+
+	return 0;
+}
+
+int timer_init(void)
+{
+	u32 *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+	*cntcr = 0x1;			/* enable clock for timer */
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
diff --git a/boards.cfg b/boards.cfg
index 69c8936..c2defb4 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -44,6 +44,7 @@
 ###########################################################################################################
 
 Active  aarch64     armv8          -           armltd          vexpress64          vexpress_aemv8a                      vexpress_aemv8a:ARM64                                                                                                             David Feng <fenghua at phytium.com.cn>
+Active  aarch64     armv8          fsl-lsch3   freescale       ls2100a_emu         ls2100a_emu                          ls2100a_emu:ARM64,EMU                                                                                                             York Sun <yorksun at freescale.com>
 Active  arc         arc700         -           synopsys        -                   axs101                               -                                                                                                                                 Alexey Brodkin <abrodkin at synopsys.com>
 Active  arc         arc700         -           synopsys        <none>              arcangel4                            -                                                                                                                                 Alexey Brodkin <abrodkin at synopsys.com>
 Active  arc         arc700         -           synopsys        <none>              arcangel4-be                         -                                                                                                                                 Alexey Brodkin <abrodkin at synopsys.com>
diff --git a/include/configs/ls2100a_emu.h b/include/configs/ls2100a_emu.h
new file mode 100644
index 0000000..dce25bd
--- /dev/null
+++ b/include/configs/ls2100a_emu.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS2_EMU_H
+#define __LS2_EMU_H
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LSCH3
+#define CONFIG_LS2100A
+#define CONFIG_GICV3
+
+/* Link Definitions */
+#define CONFIG_SYS_TEXT_BASE		0x30000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+#define CONFIG_IDENT_STRING		" LS2100A-EMU"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2100A-EMU"
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
+#define CONFIG_SYS_FSL_DDR_EMU		/* Support emulator */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+#define SPD_EEPROM_ADDRESS1     0x51
+#define SPD_EEPROM_ADDRESS2     0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
+
+#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
+
+/* SMP Definitions */
+#define CPU_RELEASE_ADDR		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		12000000	/* 12MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX       2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* IFC */
+#define CONFIG_FSL_IFC
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/*
+ * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
+ * address 0. But this region is limited to 256MB. To accommodate bigger NOR
+ * flash and other devices, we will map CS0 to 0x580000000 after relocation.
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
+ */
+#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
+#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(10)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+/* Command line configuration */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* Physical Memory Map */
+/* fixme: these need to be checked against the board */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+#define CONFIG_SYS_CLK_FREQ	133333333
+
+
+#define CONFIG_NR_DRAM_BANKS		2
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581200000\0"		\
+	"kernel_load=0x806f0000\0"		\
+	"kernel_size=0x1000000\0"		\
+	"console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS			"console=ttyS1,115200 root=/dev/ram0 " \
+					"earlyprintk=uart8250-8bit,0x21c0600"
+#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
+					"$kernel_size && bootm $kernel_load"
+#define CONFIG_BOOTDELAY		1
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x1000
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT		"> "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#endif /* __LS2_EMU_H */
-- 
1.7.9.5




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