[U-Boot] [PATCH v2 4/9] sunxi: initial generic sun7i cpu, board and start of day support
Ian Campbell
ijc at hellion.org.uk
Fri Mar 21 22:54:21 CET 2014
This has been stripped back for mainlining and supports only sun7i. These
changes are not useful by themselves but are split out to make the patch sizes
more manageable.
As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
Almo Nito
Carl van Schaik
FUKAUMI Naoki
hehopmajieh
j
Sergey Lapin
Tom Cubie
Signed-off-by: Aleksei Mamlin <mamlinav at gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Signed-off-by: Chen-Yu Tsai <wens at csie.org>
Signed-off-by: Emilio López <emilio at elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Signed-off-by: Henrik Nordstrom <henrik at henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske at gmail.com>
Signed-off-by: Luc Verhaegen <libv at skynet.be>
Signed-off-by: Luke Leighton <lkcl at lkcl.net>
Signed-off-by: Oliver Schinagl <oliver at schinagl.nl>
Signed-off-by: Patrick Wood <patrickhwood at gmail.com>
Signed-off-by: Stefan Roese <sr at denx.de>
Signed-off-by: Wills Wang <wills.wang.open at gmail.com>
Signed-off-by: Ian Campbell <ijc at hellion.org.uk>
---
v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c "sunxi: mmc:
checkpatch whitespace fixes" with v2014.04-rc2 merged in:
- just init dram once
- remove clock ramping until power control is implemented
- add CONFIG_SUN7I to simplify future SUN?I support.
- fix a typo
v1: Based on u-boot-sunxi.git#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash
section in ldscripts" vs v2014.01.
---
arch/arm/cpu/armv7/sunxi/Makefile | 11 +++
arch/arm/cpu/armv7/sunxi/board.c | 88 ++++++++++++++++++++++++
arch/arm/cpu/armv7/sunxi/cpu_info.c | 19 ++++++
arch/arm/cpu/armv7/sunxi/start.c | 1 +
arch/arm/include/asm/arch-sunxi/cpu.h | 122 ++++++++++++++++++++++++++++++++++
board/sunxi/Makefile | 11 +++
board/sunxi/board.c | 57 ++++++++++++++++
7 files changed, 309 insertions(+)
create mode 100644 arch/arm/cpu/armv7/sunxi/board.c
create mode 100644 arch/arm/cpu/armv7/sunxi/cpu_info.c
create mode 100644 arch/arm/cpu/armv7/sunxi/start.c
create mode 100644 arch/arm/include/asm/arch-sunxi/cpu.h
create mode 100644 board/sunxi/Makefile
create mode 100644 board/sunxi/board.c
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 3485404..d85b647 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -9,5 +9,16 @@
#
obj-y += timer.o
obj-y += dram.o
+obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += cpu_info.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_FEL
+obj-y += start.o
+endif
+endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
new file mode 100644
index 0000000..4a29b4b
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik at henriknordstrom.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang at allwinnertech.com>
+ *
+ * Some init for sunxi platform.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <serial.h>
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#endif
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/timer.h>
+
+#ifdef CONFIG_SPL_BUILD
+/* Pointer to the global data structure for SPL */
+DECLARE_GLOBAL_DATA_PTR;
+
+/* The sunxi internal brom will try to loader external bootloader
+ * from mmc0, nand flash, mmc2.
+ * Unfortunately we can't check how SPL was loaded so assume
+ * it's always the first SD/MMC controller
+ */
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+/* No confirmation data available in SPL yet. Hardcode bootmode */
+u32 spl_boot_mode(void)
+{
+ return MMCSD_MODE_RAW;
+}
+#endif
+
+int gpio_init(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+/* do some early init */
+void s_init(void)
+{
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I
+ /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #0x40\n"
+ "mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+
+ clock_init();
+ timer_init();
+ gpio_init();
+
+#ifdef CONFIG_SPL_BUILD
+ gd = &gdata;
+ preloader_console_init();
+
+ sunxi_board_init();
+#endif
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
new file mode 100644
index 0000000..b4c3d5c
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang at allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ puts("CPU: Allwinner A20 (SUN7I)\n");
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/start.c b/arch/arm/cpu/armv7/sunxi/start.c
new file mode 100644
index 0000000..6b392fa
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/start.c
@@ -0,0 +1 @@
+/* Intentionally empty. Only needed to get FEL SPL link line right */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
new file mode 100644
index 0000000..9330058
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang at allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_H
+#define _SUNXI_CPU_H
+
+#define SUNXI_SRAM_A1_BASE 0x00000000
+#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
+
+#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
+#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
+#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
+#define SUNXI_SRAM_D_BASE 0x01c00000
+#define SUNXI_SRAM_B_BASE 0x01c00000 /* 64 kiB (secure) */
+
+#define SUNXI_SRAMC_BASE 0x01c00000
+#define SUNXI_DRAMC_BASE 0x01c01000
+#define SUNXI_DMA_BASE 0x01c02000
+#define SUNXI_NFC_BASE 0x01c03000
+#define SUNXI_TS_BASE 0x01c04000
+#define SUNXI_SPI0_BASE 0x01c05000
+#define SUNXI_SPI1_BASE 0x01c06000
+#define SUNXI_MS_BASE 0x01c07000
+#define SUNXI_TVD_BASE 0x01c08000
+#define SUNXI_CSI0_BASE 0x01c09000
+#define SUNXI_TVE0_BASE 0x01c0a000
+#define SUNXI_EMAC_BASE 0x01c0b000
+#define SUNXI_LCD0_BASE 0x01c0C000
+#define SUNXI_LCD1_BASE 0x01c0d000
+#define SUNXI_VE_BASE 0x01c0e000
+#define SUNXI_MMC0_BASE 0x01c0f000
+#define SUNXI_MMC1_BASE 0x01c10000
+#define SUNXI_MMC2_BASE 0x01c11000
+#define SUNXI_MMC3_BASE 0x01c12000
+#define SUNXI_USB0_BASE 0x01c13000
+#define SUNXI_USB1_BASE 0x01c14000
+#define SUNXI_SS_BASE 0x01c15000
+#define SUNXI_HDMI_BASE 0x01c16000
+#define SUNXI_SPI2_BASE 0x01c17000
+#define SUNXI_SATA_BASE 0x01c18000
+#define SUNXI_PATA_BASE 0x01c19000
+#define SUNXI_ACE_BASE 0x01c1a000
+#define SUNXI_TVE1_BASE 0x01c1b000
+#define SUNXI_USB2_BASE 0x01c1c000
+#define SUNXI_CSI1_BASE 0x01c1d000
+#define SUNXI_TZASC_BASE 0x01c1e000
+#define SUNXI_SPI3_BASE 0x01c1f000
+
+#define SUNXI_CCM_BASE 0x01c20000
+#define SUNXI_INTC_BASE 0x01c20400
+#define SUNXI_PIO_BASE 0x01c20800
+#define SUNXI_TIMER_BASE 0x01c20c00
+#define SUNXI_SPDIF_BASE 0x01c21000
+#define SUNXI_AC97_BASE 0x01c21400
+#define SUNXI_IR0_BASE 0x01c21800
+#define SUNXI_IR1_BASE 0x01c21c00
+
+#define SUNXI_IIS_BASE 0x01c22400
+#define SUNXI_LRADC_BASE 0x01c22800
+#define SUNXI_AD_DA_BASE 0x01c22c00
+#define SUNXI_KEYPAD_BASE 0x01c23000
+#define SUNXI_TZPC_BASE 0x01c23400
+#define SUNXI_SID_BASE 0x01c23800
+#define SUNXI_SJTAG_BASE 0x01c23c00
+
+#define SUNXI_TP_BASE 0x01c25000
+#define SUNXI_PMU_BASE 0x01c25400
+#define SUNXI_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */
+
+#define SUNXI_UART0_BASE 0x01c28000
+#define SUNXI_UART1_BASE 0x01c28400
+#define SUNXI_UART2_BASE 0x01c28800
+#define SUNXI_UART3_BASE 0x01c28c00
+#define SUNXI_UART4_BASE 0x01c29000
+#define SUNXI_UART5_BASE 0x01c29400
+#define SUNXI_UART6_BASE 0x01c29800
+#define SUNXI_UART7_BASE 0x01c29c00
+#define SUNXI_PS2_0_BASE 0x01c2a000
+#define SUNXI_PS2_1_BASE 0x01c2a400
+
+#define SUNXI_TWI0_BASE 0x01c2ac00
+#define SUNXI_TWI1_BASE 0x01c2b000
+#define SUNXI_TWI2_BASE 0x01c2b400
+
+#define SUNXI_CAN_BASE 0x01c2bc00
+
+#define SUNXI_SCR_BASE 0x01c2c400
+
+#define SUNXI_GPS_BASE 0x01c30000
+#define SUNXI_MALI400_BASE 0x01c40000
+#define SUNXI_GMAC_BASE 0x01c50000
+
+/* module sram */
+#define SUNXI_SRAM_C_BASE 0x01d00000
+
+#define SUNXI_DE_FE0_BASE 0x01e00000
+#define SUNXI_DE_FE1_BASE 0x01e20000
+#define SUNXI_DE_BE0_BASE 0x01e60000
+#define SUNXI_DE_BE1_BASE 0x01e40000
+#define SUNXI_MP_BASE 0x01e80000
+#define SUNXI_AVG_BASE 0x01ea0000
+
+/* CoreSight Debug Module */
+#define SUNXI_CSDM_BASE 0x3f500000
+
+#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
+
+#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
+
+#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+extern void sunxi_reset(void);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _CPU_H */
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
new file mode 100644
index 0000000..559112e
--- /dev/null
+++ b/board/sunxi/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2012 Henrik Nordstrom <henrik at henriknordstrom.net>
+#
+# Based on some other board Makefile
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y += board.o
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
new file mode 100644
index 0000000..328334a
--- /dev/null
+++ b/board/sunxi/board.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik at henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang at allwinnertech.com>
+ *
+ * Some board init for the Allwinner A10-evb board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* add board specific code here */
+int board_init(void)
+{
+ int id_pfr1;
+
+ gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
+
+ asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
+ debug("id_pfr1: 0x%08x\n", id_pfr1);
+ /* Generic Timer Extension available? */
+ if ((id_pfr1 >> 16) & 0xf) {
+ debug("Setting CNTFRQ\n");
+ /* CNTFRQ == 24 MHz */
+ asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void sunxi_board_init(void)
+{
+ unsigned long ramsize;
+
+ printf("DRAM:");
+ ramsize = sunxi_dram_init();
+ printf(" %lu MiB\n", ramsize >> 20);
+ if (!ramsize)
+ hang();
+}
+#endif
--
1.8.5.3
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