[U-Boot] [PATCH v2 2/9] sunxi: initial sun7i pinmux and gpio support

[Ian Campbell]

On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
> > +     cfg = readl(&pio->cfg[0] + index);
> > +     cfg &= ~(0xf << offset);
> > +     cfg |= val << offset;
> > +
> > +     writel(cfg, &pio->cfg[0] + index);
> 
> clrsetbits_le32() here.

I looked at this transform in a few different contexts and one concern I
had was that readl and writel have barriers in them (after the read and
before the write respectively) while clrsetbits and friends do not. I
don't think this will matter for the read/modify/write bit twiddling
itself (since there are register dependencies) but I was slightly
concerned that the barriers were hiding the lack of explicit barriers
which would be required between the various reads/writes. 

But I think I am probably being overly cautious here and the obvious
transformation can be made. Anyone got any thoughts?

Ian.